UCC2897A: Inquiries about skip the switching puls

Hello Charles,
What was the issue you found with the PMP20878 reference design ?
Regards
John

Hello Charles,
Sorry but there was some issues with the E2E forum and I could not view your posting.
I can view it properly now.

L6 is a filtering inductor on the bias supply for the UCC2897A and C46 is a DC decoupling capacitor on the auxiliary gate drive FET.
I think you mean that L6 is not fitted and the value of C49 is changed from 0.1uF to two 22uF capacitors.
When this happens the startup waveform skips pulses.
Is this correct ?
Then the value of C49 (not C46 as you write) is changed to 10uF (again with not L6 fitted) and the startup is smooth.
Is this correct ?

Regards
John

Hello John
Yes, you are right.

Hello. John
Customer is dissatisfied with late response.
They requested that get response within this week.
If you want, I will share customer circuit for you.
However, I can only share by email.
I hope you will try to give me a solution this week.
Thank you.

Charles,
VDD has an absolute max rating of 16.5V and it look like this limit is being reached in this firs scope waveform.
At startup the voltage on the auxiliary winding will peak charge C49. The leakage inductance will tend to give an overvoltage on C46.
L6 will act to smooth out this spike so removing L6 is not a good idea. You can replace L6 with a small resistor (less than 100 Ohm value)
Reducing the value of C49 also helps to quickly dissipate this peak voltage.
So your options are to add a small LC or RC filter, reduce the leakage on the auxiliary winding or add a small linear regulator on the supply.
This should give a smooth startup

Dear John

The VDD max voltage in this circuit is 14.7V and the IC limit voltage does not reach 16.5V.
In addition, the Vdd voltage at initial start-up is supplied by the internal regulator of the TPS2373-4 IC.
When after start-up, it supplied to the transformer auxiliary power supply.
The voltage to transformer auxiliary is approximately 12V.
And they designed 22ohm for L6 location.

1. Why skip the switch when Vdd is higher then typical UVLO Voltage(8V) of the UCC2897?

2. Why do not happen to skip the switch when C64 changed 10uF to 44uF(22uF*2ea)?

3. If VDD of the UCC2897 is 16.4V, is it stop the switching?

There is an error in the previous question, so please correct it as follows.
I misrepresented C64 as C46.
So check please that "Why do not happen to skip the switch when C64 changed 10uF to 44uF(22uF*2ea)?"

Please check and reply.
My customer tired to wait long time.

Hello Charles,

If my understanding  of events is accurate you have modified that part of the circuit which only provides bias power to the UCC2897A
In one configuration there is an issue and in another configuration there is no issue.
If this assessment is accurate then my conclusion is that the voltage is not the correct level required by the UCC2897A.

But since you have not provided a full schematic of the design with accurate scope plots there may well be other factors influencing the result of this test.
With the data provided my belief is that there is an issue with the voltage on the VDD input causing a start up issue and that is where you should focus your attention.
Please let me know the results of these tests.

Regards

John

Hello Charles,

We contacted the designer for this reference design and this was his reply :

"We have found some issues with this design when using the start-up regulator in the TPS2373 PD controller.  I am going to look at this later next week in the lab.  I can better answer the E2E post once I have done some testing.

Thanks,

David Strasser"

As he promised he will reply to your post next week

Dear Griffin

If you completed to check about the start-up regulator in the TPS2373, please share result to me.

Thank you.