My application is a basic 5S configuration, very similar to the basic configuration of the demo board but with a 20A OCD1 trip. I have designed and layed out my own PC board so this troubleshooting is on that. I'm using a 3mOhm current sense to develop the 60mV @ SRP & SRN. My problem is that I can not get the IC to trip (turn off discharge FETs) at all when an OC load is applied. As a test, I even increased the sense resistor to 10mOhm which should cause it to trip @ 6A but still nothing. The EVAL board I have, which is set for approx. 4A tirp, does trip in my test configuration with no problem.
I'm using a Kelvin connection at the sense resistor and I routed these traces to SRN & SRP as if they were diff pair, together and keep them away from other routing. The filtering components are the same as listed in appnotes and on demo board and are placed very close to the IC pins (10 & 11).
I see the sense voltage at the IC pins, no problem when the load is heavy enough to exceed 60mV, nothing happens..... the load is still supplied....even when I double the load I have tried different resistor values on the OCDP pin (detection delay). I even cut away my SRN & SRP traces and jumpered-in a small length (~ 2.5 inches) directly from the sense resistor to RC filter input right at the IC pins.
I'm using an electronic load in constant current (CC) mode to execute this test. I have actual 18650 cells attached to the circuit.
It's as if the lot of ICs that I received from our supplier has the OCD features disabled in the EPROM settings. My next step is to actually remove the IC from the demo board and install it on my board. Yes, it has come to that. So, I'm looking for ideas.
