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TPS25944L: Two level efuse

Part Number: TPS25944L
Other Parts Discussed in Thread: TPS25944A

Hi, 

I have an application that can be either powered from USB or external power adapter. Depending on if there is external power or not i would like to increase the efuse current limit. 

I have made the following (simplified) circuit:

A comparator is used to detect if external power adapter is preset, which in turn enables Q1. 

I know this is not the typical application and its also likely to be the reason for the odd behavior i get from this circuit because of this, which is the following:

1) The default condition is USB powered, which uses only RB to set ILIM.

2) If external power is connected RA is put in parallel to RB changing the limit (increasing ILIM). which works fine.

3) If than the load is adjusted to somewhere in the new higher limit range, and external power adapter is removed. ILIM is changed back to the lower limit with only RB. In this situation the efuse seems to trip as expected (disable output), but the fault pin did not change state to fault condition (It seems like there is only rising edge flank current detection to generate the over-current fault condition?).

A solution would be to give a reset pulse in case external power is removed, but this also disconnects the load for the pulse duration which in case of a "light load which could be USB powered" is undesired. 

Does anyone know if there's a easy workaround for this issue?

Regards,

Ivo

  • Hi Ivo,

    Welcome to E2E!

    In STEP-3, when external power adapter is removed, which source is powering TPS25944L input +3V3?
    Or do you mean when supply voltage of external power adapter is decreased ?

    Can you share test waveform of
    1. input voltage, Gate signal of Q1, output current, Fault output
    2. input voltage, Gate signal of Q1, output current, Output voltage.

    Best Regards,
    Rakesh
  • Hi Ivo,

    Any update on the test waveforms

    Best Regards,
    Rakesh
  • Hello Rakesh,

    Sorry for the delay. 

    There are two possible power sources; USB and / or a +5V ACDC adapter. They are "OR'ed by diodes to a common +5V rail. This rail is used to power a DCDC converter that generates the system's +3V3, which is also connected to the efuse input.

    I don't have any waveforms available but the gate signals of Q1 are logic levels from a comparator used to detect external power before the ORing diode.

    This version of the chip requires at least 4ms duration of overload before its triggered by over-current, we use the fault pin to trigger a reset after a x delay and besides that our load is dynamic. Because of this sometimes it does not meet the requirement to trip where we assumed it would trip. This gave me the wrong impression about fault pin state not being in sync with the efuse switch state.

    I have the impression that going from the high limit (RA//RB) to low limit (RB) only works when a reset pulse is provided after switching limits  in case there is already a high level load connected. So it seems the only solution is to give a reset pulse once external power is removed to guarantee correct behavior under all conditions ( USB Power + no load / light load / high load, EXT power + no load / light load / high load, USB + EXT power + no load / light load / high load).

    Due to limited time i will test this a bit more somewhere next week. 

    Best Regards,

    Ivo

  • Hi Ivo,

    Understood.
    Does the auto-retry version of the device TPS25944A helps you?
    I will look forward for update on your testing.

    Best Regards,
    Rakesh
  • Hi Ivo,

    If you anticipate more delay in testing. Please close this thread and feel free to open a new thread.

    Best Regards,
    Rakesh
  • Hello Rakesh,

    The solution to this problem was to increase the current limit slightly to make sure that our "dynamic" load was not tripping Ifastrip (which is related to ILIM). This was causing the strange behavior, now everything works as intended. 

    Best Regards,

    Ivo