Hi Team
I want adjustable rise time. TPS22975 Datasheet P.15 Vout rising time formula is Vbias =5V.
SR = 0.43 * Ct + 26
But my Vbias = 3.3V.
How did I calculate the slew rate ? same Calculation formula ?
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Hi Team
I want adjustable rise time. TPS22975 Datasheet P.15 Vout rising time formula is Vbias =5V.
SR = 0.43 * Ct + 26
But my Vbias = 3.3V.
How did I calculate the slew rate ? same Calculation formula ?
Hi Kerr Chang,
For the TPS22975, we did not take the data for VBIAS=3.3V, but as an estimate I used VBIAS=5V and VBIAS=2.5V data to come up with the following equations for VBIAS=3.3V:
VIN=3.3V: tR(us) = 2.14 x CT(pF) + 136
VIN=2.5V: tR(us) = 1.65 x CT(pF) + 110
VIN=1.8V: tR(us) = 1.23 x CT(pF) + 88
VIN=1.05V: tR(us) = 0.773 x CT(pF) + 63.9
Again, please note that these are good for estimations, but process and temperature variation may cause some deviations from the equations.
Thanks,
Alek Kaknevicius
Hi Joey and Shaq,
Since TON doesn't affect the timing characteristics of our load switches, you can use the equation that Alek provided above to calculate the rise time: VIN=3.3V: tR(us) = 2.14 x CT(pF) + 136
Regarding the tolerance to these equations, what type of accuracy are you expecting (ex:25%, 50%)? Does this rise time need to be accurate across temperature?
I just looked up some lab data we took across 5 devices, and it looks like for the temperature range of -40C to 105C we see a maximum deviation of 10%. However, we cannot guarantee that the deviation won't be larger since there are many things which can affect rise time (device variation, temperature, CT capacitor variation, board layout).
Thanks,
Arthur Huang
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Hi Shaq,
We normally don't spec tdelay for each VBIAS / VIN condition, but we were able to pull some information from our characterization data. Please find a chart below that shows the tdelay time across CT:
CT | VIN = 3.3V |
0pF | 75 |
220pF | 215 |
470pF | 334 |
1000pF | 552 |
2200pF | 1088 |
4700pF | 2048 |
10000pF | 4531 |
Using this data, the following equation can be used to extrapolate the tD time (for CT > 0pF):
VIN=3.3V: tD = 0.438 x CT(pF) + 104.4
Thanks,
Arthur Huang
Hi Arthur,
Customer test the delay time on their PCB.
Result as below:
According to the tD equations .
VIN=3.3V: tD = 0.438 x CT(pF) + 104.4 = 0.438 x 3300pF + 104.4 = 1549.8us.= 1.549ms.
Consider the variation of capacitor (+-10%) / High Temperature(-12%) / equation (+-10%).
The worst case calculation is 1.863ms ( max )
But the actual measurement tD is 2.48ms.
Customer want to know why this variation is so high.
Thanks
Shaq.
Hi Shaq,
Thanks for providing additional details. The delay time of the load switch can also be affected by the load resistance and the load capacitance. If you have a larger output resistance, it will require more gate drive until the output voltage starts to rise. For reference, you can refer to section 2.2 and 2.3 of our app note, Timing of Load Switches, for additional details.
Have you been able to try a similar configuration on the EVM? What tdelay times are you seeing there?
Thanks,
Arthur Huang