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TPS63070: What is best grounding practice for TPS63070 IC?

saiteja manchukanti
Intellectual 330 points
Part Number: TPS63070

Hello, 

I am using TPS63070 IC in an application. As per datasheet, TPS63070 has two grounds namely PGND(pin 10) and control ground(pin 4).  Apart from these two pins I am also connecting VSEL(pin 15) and FB2(pin 2) to  ground.  Kindly answer below two question regarding my design.

1) Am I suppose to connect VSEL (pin 15) and FB2 (pin 2) to PGND(pin 10) directly?

2) Am I suppose to connect VSEL (pin 15) and FB2 (pin 2) to GND(pin 4) directly?

2) Can I connect PGND(pin 15) to common ground plane of my circuit ? 

3) Can I connect GND (pin 4) to common ground plane of my circuit ?

Link for datasheet : www.ti.com/.../tps63070.pdf

Kindly help me in this regard.

Regards,

Sai Teja.

  • 0
    TI__Expert 7925 points
    Hi Sai Teja,

    For the recommended layout you can take a look at the datasheet recommendations and the EVM layout. To answer your questions:
    1, 2) It is recommended to connect both VSEL and FB2 to GND pin. VSEL is not that critical and can also go to PGND pin or plane.
    3, 4) You can connect both GND and PGND to common ground plane of your circuit. But first make sure that you have a local center ground point close to the device PGND and the I/O capacitors, like on the EVM.

    Best regards,
    Milos
  • 0 in reply to Milos
    Intellectual 330 points

    Hi Milos,

    Thanks for your reply.

    May I know what do you mean by local center ground point  close to device PGND ?

    In EVM, the common ground plane is connected to PGND and control ground (pin 4) is connected to ground plane (PGND) at one point.

     In similar way, In my design I directly connected PGND to common ground plane. And I connected control ground(pin 4) to common ground plane at one point. Please find attached image of boost block in the design. 

    Also note that common ground plane is also directly connected to grounds of other blocks of circuit.

    Please let me know if any changes are need to be made in this design..

    .

    Regards,

    Sai Teja.

  • 0 in reply to saiteja manchukanti
    TI__Expert 7925 points

    Hi Sai Teja,

    The local center ground point is between C1 and C4 capacitors on the EVM, or on your PCB between those two capacitors closest to the device. Ideally, FB2 should go to GND and GND should go straight to the central ground point (but not via PGND pin). In your case the layout is similar as the EVM and that should be fine, but I would put a couple of vias there, like it is on the EVM.

    Some remarks:
    1. Seems that there is a Vout island on the bottom layer that does not serve to anything? I would expand the GND plane there instead.
    2. It looks like you are not using the PG pin, so you may leave it floating and remove the pull-up resistor.
    3. Place the GND vias as close as possible to the GND pads of I/O filtering capacitors, like it is on the EVM.

    Best regards,
    Milos

  • 0 in reply to Milos
    Intellectual 330 points

    Hi Milos ,

    Thanks for your quick reply.

    Regarding 1st remark about polygon on bottom side, I followed it because I observed output polygon on bottom side in EVM also.

    Is it okay if I remove that isolated VOUT polygon in bottom layer?

  • 0 in reply to saiteja manchukanti
    TI__Expert 7925 points
    Hi Sai Teja,

    That polygon on the EVM is not really necessary, so you can remove the one on your board. What is the output current in your application?

    Best regards,
    Milos
  • 0 in reply to Milos
    Intellectual 330 points
    Hi Milos, Output current in my application is 1 ampere.
    So, Can I remove polygon in the bottom layer?

    Regards,
    Sai Teja.
  • 0 in reply to saiteja manchukanti
    TI__Expert 7925 points
    Hi Sai Teja,

    Yes, you can remove it.

    Best regards,
    Milos