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TPS3823: RESET output is always low after a MR pulse

Jeffrey Lomibao76
Expert 1210 points
Part Number: TPS3823

Hi,

I am seeing an issue with the RESET output of the TPS3823. The RESET output stays LOW after I give it a 1ms low pulse on the MR pin. I am supplying a 400ms periodic pulse on WDI pin. And I have verified that I am getting a RESET pulse output when I disable the WDI pulse. What else am I missing?

Thanks,

Jeffrey

  • 0
    TI__Mastermind 19580 points
    Hi Jeffrey,

    Can you provide us a schematic so we can better understand the problem?

    -Marcoo
  • 0 in reply to Marcoo Z
    Expert 1210 points

    Hi Marcoo,

    Attached is the schematic. Thanks for looking into this.

    Jeffrey

  • 0 in reply to Jeffrey Lomibao76
    TI__Mastermind 19580 points
    Hi Jeffrey,

    Can you scope the WDI pin to see if WDI will reach the appropriate voltage level. This WDI pin is digital so it assumes it has no pull up or pull down and this might affect the output.

    -Marcoo
  • 0 in reply to Marcoo Z
    Expert 1210 points

    Hi Marcoo,

    Attached is the scope output. The yellow trace is the WDI, and the blue trace is the RESET.

    We have a pull-down resistor on the WDI to make sure that the watchdog will always be active.

    Thanks,

    Jeffrey

  • 0 in reply to Jeffrey Lomibao76
    TI__Genius 12630 points
    Jeffrey,

    The "issue" you are seeing is the latching feature of the TPS3823. This is described in section 8.3.4 Watchdog Timer (WDI) section on page 11 of the datasheet. To summarize, the TPS3823 will latch the /RESET output when a fault occurs and WDI is still transitioning. So in your case, you caused a reset due to /MR and WDI is still pulsing while the /RESET is active and logic low, so the /RESET will remain active and logic low.

    If the application requires that input to WDI be active when the reset signal is asserted, then either use the A version of the device or a FET should be used to decouple the WDI signal. The A version does not latch the reset signal to the asserted state if a WDI pulse is received while RESET is asserted. In the second option, an external FET decouples the WDI signal by disconnecting the WDI input when RESET is asserted as shown in Figure 11 WDI example.

    I recommend using TPS3823A for the quick fix to the latching effect you are seeing.

    Please let me know if this solves your issue. Thanks!

    -Michael