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TPSM84A21: Input current transient

Bruno B
Expert 1140 points
Part Number: TPSM84A21
Other Parts Discussed in Thread: TPS54A20

Hi,

As far as I could understand (referring to slva750a) the internal switching mechanism of this part is based upon a N steps looping machine, where only 1 step interval is dedicated to energy transfer from Input voltage to output current.

Webench simulations also help to understand that input transfer (hence input current transients) indeed occurs every other clock rising edge. Correct me if I am wrong.

Hi,

As far as I could understand (referring to slva750a) the internal switching mechanism of this part is based upon a N steps looping machine, where only 1 step interval is dedicated to energy transfer from Input voltage to output current.

Webench simulations also help to understand that input transfer (hence input current transients) indeed occurs every other clock rising edge.

My question is related to the fact that we have a lot of DC/DC converters, some of them running at a lower 1Mhz,  and we want to control the distribution of input current transient , seen by the Input voltage source (each DC/DC converter being synchronized by its dedicated clock, with dedicated phase delay)

In such case where the part is externally synchronized by a 4Mhz clock, is there a way to know which  clock rising edge does correspond to transfer energy from the input voltage ? for example odd rising edges, or even rising edge (counted from the first rising edge appearance of the external 4M clock) ?

with best regards,

Bruno

  • 0
    TI__Guru 50120 points
    Hi Bruno,

    During every switching cycle, the internal circuity controls the HIGH and LOW side MOSFETs on and off. When the HIGH side is ON and LOW side is OFF energy is transferred from the input power supply through the HIGH side MOSFET then through the inductor to store the energy. When the LOW side MOSFET is ON the inductor releases energy to the output.

    If you are wondering at what point in the switching frequency does the input supply provides energy for the inductor to store, then the answer is when the HIGH side FET is ON. That moment occurs when SW node is HIGH.

    Regards,
    Jimmy
  • 0 in reply to Jimmy Hua
    Expert 1140 points
    Hi Jimmy,


    Thank you for the reply,

    I perfectly understand your comments, which seem to apply for common synchronizable buck converters. For such common buck, the energy transfer is often triggered by external clock rising_edge, each individual rising_edge triggering the high side mosfet ON. In that case there is a clear relation between the clock edge, and the SW node being High.

    For the TPSM84A21 the situation looks quite different since as far as I could understand the energy transfer from input voltage occurs 1 cycle over 2, that is at 2MHz, the external clock being 4Mhz.Therefore when looking at the 4MHz external synchronization clock (the only observable signal) , there is the uncertainty of knowing which cycle IS the cycle dedicated to energy transfer from input.

    My question is more about to be able to identify which external 4MHz clock rising_edge DOES trigger energy transfer from the input.

    Also note that for the TPSM84A21 there is no SW pin available to external observation, and also that there are several inductors and mosfet inside.


    With best regards,

    Bruno
  • 0 in reply to Bruno B
    TI__Guru 50120 points

    Hi Bruno,

    The internal IC to this power module is the TPS54A20. If you look at Figure 37 you will see the switching waveform of each path(SWA and SWB). The output that the capacitor will see is the combination of the two switching paths(imagine overlaying the two). This means that the moment of energy transfer between power supply to output is during the rising edge of every pulse train. The two paths will be 180 degree phase shifted. I believe the conventional understanding of buck converters still apply in this case. Let me know what you think. 

    Regards,

    Jimmy 

  • 0 in reply to Jimmy Hua
    Expert 1140 points
    Hi Jimmy,

    Thank you for sharing your knowledge.
    What I can see from figure 55 is that energy transfer from power supply is performed only when SWA is high. This also corresponds to figure 44 time interval.
    The rate is therefore 2Mhz while the clock is 4 Mhz.
    Don't you agree ?

    Regards,
    Bruno
  • 0 in reply to Bruno B
    TI__Guru 50120 points
    Hi Bruno,
    Thanks for the clarification. Looking at Figure 55, it would appear that SWA has a larger impact on the input voltage ripple than SWB. In this case, putting a input "pi-filter" centered at 2Mhz should help reduce the noise.

    Regards,
    Jimmy
  • 0 in reply to Jimmy Hua
    Expert 1140 points

    OK Jimmy,

    We now agree that SWA is being activated at the rythm of 1 every other clock cycle.

    My very first concern was the correlation between SWA activation and the external clock rising edge.

    Hence the question : Is there a deterministic correlation between the (internal) SWA activation (2Mhz rate) and the (external) first rising edge appearing at the SYNC input (4Mhz rate) ?

    best regards,

    Bruno

  • 0 in reply to Bruno B
    TI__Guru 50120 points
    Bruno,

    From my understanding the SWA activation will lock onto the first rising edge of the external SYNC input and produce a switching of half the oscillating frequency. The SWB activation will be 180 degree phase shifted of the SWA. So the correlation is when the SYNC input is initial applied the converter will force SWA to lock onto the initial rising edge.

    Regards,
    Jimmy
  • 0 in reply to Jimmy Hua
    Expert 1140 points
    Hi Jimmy,

    You have answered to my question.
    Thank's for your support.

    Regards,
    Bruno