LM5116: latch off problem

Hi Support,

The voltage at EN pin is very stable during latch off.  In most of the cases, the latch off cannot recover until the input voltage off-on again. However, in one case, the buck converter will recover after a few hours.

For your information, the frequency is around 110kHz, the load is 5.6V/10A with peak 18A. The OCP point is 22A. The input voltage is 20-31.5V.

Thousands of our products (telecom system) are installed in many locations and most of them are very far.   A few percentage of them got this problem randomly. Now we are facing big problem and need your expertise. Kindly give your hand to guide us to find the root cause.

Thank you!

Zhang Binbin4174.LM5116_quickstart.xls

This is the schematic drawing:

Hi Binbin, ikon,

The internal UVLO pull down NMOS is latched on when a VCC UVLO occurs or the hiccup counter expires (ILIM). It will release when the VCC UVLO clears and UVLO < ~200mV.

Note UVLO must pull below ~200mV for the latch to release. The pull-down FET is about 100 Ohms typical. If the impedance at the UVLO pin is too low, the LM5116 may not be able to pull UVLO low enough to reset the latch and the part could stay off.

Maybe you can check the behavior of UVLO from this standpoint.

Regards,
Tim

Hi Tim,

Thank you for your reply!

We understand that the 100 Ohms Mosfet will be triggered on and then pull low UVLO pin at 4 conditions such as UVLO at Vcc, UVLO at HB, OTP and OCP for 256 cycles.  But  LM5116 will restart once UVLO pin is below 200mV & temperature < 155 degreeC, according to LM5116 datasheet. Our mentioned case is that UVLO pin is always 0V (upon measurement, the resistance between Pin 2 & Gnd is 80+ ohm) and the buck converter is always off. The voltage of all other pins (EN, Vin, VccX & Vcc etc) can meet re-start condition.

I wonder whether there is a hidden condition for LM5116 to keep at latch status. Kindly share with us your expertise again.

Thank you!

Best Regards from ZHANG Binbin

Hi Tim,

Thank you for your suggestion!

Please let me share a bit the background for this issue: we found the latch problem cases in field, and is trying to repeat the latch in our lab so as to work out a solid solution. But so far we do not have the luck.

We tested with or without the discharging diode and could not repeat the latch problem today. I believe that this diode is used to force the converter to shutdown if Vin goes low, otherwise, the converter may work at very low Vin voltage (as UVLO still high) and may cause over stress on some components. Our test shows that it is not an issue for our application as we keep big margin for the external components.

I revisited the datasheet again and found two descriptions as follows:

1. Page 15, "The maximum EN transition time for proper operation is one switching period. For example, the enable rise time must be less than 4 μs for 250-kHz operation." We tried to slow down the rising of EN, the Buck converter can re-start properly. I wonder what will the possible outcome be if the mentioned condition violated.  

2. Page 15, "At higher switching frequency (greater than approximately 250 kHz) the hiccup timer may be disabled if the fault capacitor is not used." Although the frequency is 110kHz and fault capacitor is present (0.22uF) in our converter, I wonder whether the disabled hiccup timer (for 256 cycles counting? please confirm) will cause latch (cannot re-start) if the mentioned conditions occurs. 

Look forward to your reply and wish you a nice weekend.

Best Regards from ZHANG Binbin