UCC27714: HB,HS,HO leakage failure

Hi Richard,

Richard Herring said:

The competitor part that is rated at 600mA sink current may have been rated at a higher VDD/VHB voltage

VCC=25v absolute MAX, 20v recommended, VB=VS+20v. Does TI recommend +12 VDD over that of +15 VDD for <20 VGS NFETS?

Richard Herring said:

The other driver you mention is a 350mA source/ 600mA sink driver, please confirm if not correct

GTon=120ohms, GToff=60 ohms same parallel Schottky with no (0) Qrr over shooting B+. This may be due to bipolar PWM switching as the Qrr ringing occurred mid supply, not top supply as it now does! That is the one major difference noticed between the competitions gate driver. Perhaps why we never saw any overshooting spikes into B+ and Schottky HS to AGND was to stop parasitic currents causing HI latch ups.

Richard Herring said:

In this case, the UCC27714 with higher drive current may have higher sink current with the 24 Ohm turn off resistance, in your application at 13.6V VHB. This may result is some additional ringing on the Vgs.

There are no external Totem poles BJT's.  Values less then 24 ohms (GToff) short UCC HO/HS very quickly during open loop commutation cycles. Actually increased from 75 ohm up to 130 GTon has proven more prudent in protecting HO/HS stresses. Initially was stressing HO/HS on all three 1/2 bridges more frequently via 6-12ohm GToff thus created excessively high DS Tr overshooting on HV.  Also just removed 1uf caps Pin 5 AGND to VDD. Guessing 1uf to AGND perhaps injects delta winding Thriten harmonic PWM transients into VDD causing part of the (random) DS overshoot onto HVDC B+.

Richard Herring said:

If there is HO to HS negative ringing, I would suggest the HO to HS schottky diode to limit the negative ring, to see if these resolve the issues.

The GToff undershoot ringing was minimal (<-4v) at 80-100vdc supply. Just replaced 24 ohm with 51ohm Gtoff and have not yet checked the difference. Checking LO/HO outputs the center (new UCC) at times HO crosses LO near 10v even with 60-80ns dead band.  Again why does first HO pulse occur yet does not on the other 1/2 bridges until after 2nd pulse and notice all HO pulses seem to occur mid Cboot charge rise time. That rising edge 1st pulse HO (CH2) during Cboot charge cycle seems to occur far to early does it not? At what level does HO/LO crossing cause shoot through? Suspect where HO/LO randomly cross 10v (yellow circle)  HO is actually just above LO. If shoot through is occurring might it explain HO/HS leakage path development but not blow fuses or short 80 amp NFETS?

No inductors three bridges, center shown open loop commutated. Notice 1st pulse cycle rise time cut short and others start charging Cboot after PW occurs.

Richard Herring said:

On question 3, is there just an HO to HS higher leakage current failure in the application, or does the HO output stop generating output pulses

Being leakage was in the center phase it may have gone unnoticed until doing DMM to GND check but typically the resulting pulse is to much greater. Later check if UCC was causing fault trips during open loop commutation after HV transient suffered MCU VDD rail in the process. Leakage HV being the one attribute where 24v can multiply into over 90v peaks, with an inductor the NFET pulses peak well over B+.

Leaky UCC: diode check HO-HS reads 1.29v drop, reverse leads 0.697v. 

Hi Richard,

Richard Herring said:

On question 3, is there just an HO to HS higher leakage current failure in the application, or does the HO output stop generating output pulses. High leakage current on HB or HO will discharge the HB cap which can terminate the HO pulse due to UVLO before HI goes low

Zoom in on the HI HO signals all 3 UCC are similar short HO. Seemingly HI signal saturates Cboot with 50us pulse on HI, there is no UVLO in well filtered +15 VDD local bias 5.1R 10uf. One reason ? forum year ago why Cboot was calculated 1uf in TIDA-00778, formula in UCC datasheet suggest 122n/0.122uf Cboot.  Does zoom capture not appear as if Cboot has fully charged saturates near mid VDD, therefore stops pulsing? We don't see quite so much HO artifact as below capture during closed loop commutation as the trapezoidal wave form hides all but the recovery spikes shown above post capture.  

Hello BP101,

In this post, and the previous post scope plots, to determine the driver operation I would need to see some more detail on the waveforms, as well as other signals.

Also please confirm if the provided waveforms or with the UCC27714 driver that has the high leakage as you mention, or is not damaged yet.

On the waveform in this post, It certainly looks like the HO is declining, I assume to HB discharging and going into UVLO. Is the CH1 waveform the HO with respect to ground, or is it differential with respect to HS?. Can you take this waveform again with one of two methods; Record HO, HS, HB, and HI; show wide time base as you have, and also zoom out to see more cycle information on the last few cycles before HO stops switching.

On the plots shown in the previous post. It looks like this is HO with respect to ground, which is HO plus HS. Can you take those same plots showing the same HI, HO, HS and HB waveforms? I would like to confirm what HO is doing with respect to HI and HS.

Regards,

Richard Herring

HI Richard,

Richard Herring said:

On the plots shown in the previous post. It looks like this is HO with respect to ground, which is HO plus HS.

Does it really matter where the threshold of HO is referenced if Cboot is being early discharged or saturated, take your pick. We only have two cannels to work with, captures are 1KSPS deep.

Richard Herring said:

On the waveform in this post, It certainly looks like the HO is declining, I assume to HB discharging and going into UVLO

Countering that idea notice LO is not being effected by VDD droop as HO stops pulsing, abruptly overshoots VDD bias (14.7v) by 6v, peaks 36v, very early roll off relative to HI. Perhaps symptoms point to HB overcharge (saturation) more related would it not? We have also captured VDD bias during HB charge period remains very stable, if UVLO occurs it is not by external VDD circuit design. If Cboot (1uf) was being depleted at even QG 90NC what would HO look like relative to HI shown in capture? So the UVLO is auto resetting in each HO cycle during loaded inverter run time or simply reacting badly to an No inductive load condition? If the latter is occurring the current load of  any single phase is 0 every 240 degrees as only two phases commutate at any given time.

Richard Herring said:

Record HO, HS, HB, and HI; show wide time base as you have, and also zoom out to see more cycle information on the last few cycles before HO stops switching.

Why not simply reduce Cboot 100n or even 50n record what happens? The HO drop occurs early on all three gate drivers makes it unlikely UVLO is occurring from driving an unloaded NFET, does it not? Also noted inverter run time tight ringing pattern at Miller plateau, seems to indicate Cboot being suspect, seemingly not UVLO. If UVLO was occurring it would effect the ability for motor to even run under heavy load, correct?

Hi Richard,

Richard Herring said:

I would like to confirm what HO is doing with respect to HI and HS.

Ok we try different approach change Cboot 100n thus discover HI input RC filter somehow changes PWM generators PW=2.5us versus 50us, relative 1uf Cboot captures above. Does the UCC charge pump really need to exceed VDD even overshoot it each and every HO pulse? Notice with 100n Cboot first few pulses only overshoot VDD then drop down to VDD relative to GND.  Oddly the other 2 UCC (1uf Cboot) only reach VDD (14.7) bias on the first pulse, next pulses overshoot VDD >19.7v, a 5v net increase over VDD bias 10uf cap.

Checking the competitions gate driver (Cboot 1uf) HO produces similar VDD overshoot 50us pulses but does not cause excessive B+ overshoot in the NFETS as UCC last capture. That seems the primary issue to why the UCC H0-HS junction can quickly break down start leaking and Cboot cap value HO issue seems related to the Trr overshooting.

NFET Trr ringing overshoots B+ 80v not any less at 100v:

The confusing issue being Cboot 1000n limits HB-HS PW to 50us, 50% duty, no matter HI start pulses < 2.5us. Note the HO drive PW starts (2.5us) transitions into 20us PW. Yet the high HS peaks >36v first pulse, thereafter with 100n Cboot are missing in 80us PW (300ms HO period) CH2.

Seemingly no voltage regulation of HB exists to compensate for Miller PCHAN boost modification. Therefore Cboot bias (14.7v) can exceed VDD max thus cause HOPW peak concerns! There was plenty of energy (Cboot 100n) to wield 36 pound rotor in open loop commutation. However the huge EMF/EMI 1000n Cboot caused now diminished requires lower db FOC adjustments. Perhaps TIDA-00778 should reevaluate as we have the ill effects of 1000n Cboot choice, OGBT module might run more efficiently if not being over driven.