• State Resolved
  • Locked Locked
  • Replies 8 replies
  • Answers 1 answer
  • Subscribers 63 subscribers
  • Views 466 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS65218D0: accuracy of DLY when PWR_EN is disabled

Shinichi Inoue
Guru 21721 points
Other Parts Discussed in Thread: TPS65218D0

Dear Specialists,

My customer is considering TPS65218D0 and has a question.

I would be grateful if you could advise.

---

When PWR_EN is disabled, output is off after 2ms(default).

Could you please let me know the accuracy of 2ms.

Does it depend on the oscillator frequency(2400kHz)?

If so, could it possible to think 2ms +/- 12%?

---

I appreciate your great help in advance.

Best regards,

Shinichi

  • 0
    TI__Expert 8730 points
    Hi,

    I have assigned your request to responsible Applications Engineer and we will get back to you as soon as possible.

    Regards,

    Murthy
  • 0 in reply to Krishnamurthy Hegde
    Guru 21721 points
    Hi Murthy,

    Thank you for your reply.

    I'm looking forward to waiting your response.

    I appreciate your great help.

    Best regards,
    Shinichi
  • 0
    TI__Mastermind 30310 points
    Shinichi-san,

    What is your need for understanding the tolerance of this spec?

    Timing parameters are not usually tested in production because it takes too long.

    The beginning of the power-down sequence (from PWR_EN low to the first rail shutting down) is DLY9.

    All delays DLY1-DLY9 can be set to a value of 2ms (0b, default) or 5ms (1b) and the delay factor can be 1x (0b, default) or 10x (1b) such that delay times of 20ms and 50ms can also be achieved.

    The clock frequency of 2400 kHz also does not have Min or Max specs in the datasheet, but the tolerance of the clock frequency will be the same as the tolerance of the delay timing.
  • 0 in reply to Brian Berner
    Guru 21721 points

    Hi Brian,

    Thank you for your reply.

    Even if 2ms is set, there is an error.

    The customer'd like to know what percentage is it.

    I was wondering if you could advise.

    Best regards,

    Shinichi 

  • 0 in reply to Shinichi Inoue
    TI__Mastermind 30310 points

    Shinichi1 said:
    Even if 2ms is set, there is an error.

    What is the error?

    What type of processor are you powering with the TPS65218D0?

    If you are powering a Sitara (AM335x or AM4x) processor, I can assign this thread to the Processor forum so they can help resolve your error more quickly.

  • 0 in reply to Brian Berner
    Guru 21721 points

    Hi Brian,

    Thank you for your reply.

    I'm sorry for confusing you.

    The customer'd simply like to know the difference between set value(2ms) and actual value.

    They need to estimate system power up time and power down time, aren't in a problem. 

    I appreciate your great help.

    Best regards,

    Shinichi  

  • 0 in reply to Shinichi Inoue
    TI__Mastermind 30310 points
    Shinichi,

    The accuracy of the oscillator is not given in the specification, so the best I can do is offer you an estimate of the tolerance.

    A conservative estimate would be +/-20%, which means each delay would be 2ms +/- 0.4ms (1.6ms min, 2.4ms max) and the total time for the TPS65218D0 power-on sequence if all 9 delays (DLY1-9) are used would be 18ms +/- 3.6ms (14.4ms min, 21.6ms max).
  • 0 in reply to Brian Berner
    Guru 21721 points

    Hi Brian,

    Thank you for your reply.

    This is the answer the customer had requested.

    I'll share this with the customer.

    I appreciate your great help.

    Best regards,

    Shinichi