Hi,
in datasheet page 20, it says "In addition, there are two delays between RUN going high to first PWML pulse going high in each burst packet. The first delay is a fixed 2.2-μs delay time, intended to provide an appropriate wake-up time for UCC28780 and the gate driver to transition from a wait state to a run state.The second delay is another 2.2-μs timeout, tZC in the electrical table, intended to turn on the low-side switch of the first switching cycle per burst packet around the valley point of DCM ringing by waiting for the zero crossing detection (ZCD) on the auxiliary winding voltage (VAUX)."
Please help check the logic is right or not:
1. After RUN reaches to high, there will be 2.2us delay time used to weak up UCC28780;
2. After this 2.2us weak up time, there will be 2.2us timeout delay time.
3. After the the 4.4us(2.2us+2.2us) delay time, if VS pin monitor there is ZCD event, PWML will be triggered to high.
So there will be typically 4.4us delay time from RUN_high to PWML_high. Right?
But, I checked that, there is only 2.2us from RUN_high to PWML_high on my board.
Could you help explain it?
Thanks!
BR
