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BQ77915: Design Not Working

Part Number: BQ77915

Hello,

I made a PCB with the BQ77915, but the design does not seem to work.

Test setup:

-5 220ohm resistors with 18.5V psu to simulate

-PCB with BQ77915

-8 ohm load

What happens:

-No load: Output is 18.5V for a second, then drops to 16.2V

-With load: Output almost immediately collapses 

What could be the problem?

Schematic:

Q1= NVMFD5C466NLT1G

D4= BAT54C

No jumper are connected, so 5S config.

  • Hi Jesse,
    From the schematic please note the need for the RTS_PU resistor on the front page schematic or other such as figure 18. Without the resistor R26 will pull down TS and the part will go to a UTD condition. tOTD_DELAY is about 4.5s though.
    If the delay is 1S to a change in output voltage it sounds like it could be an undervoltage protection. Check that the simulated cell voltages are getting to the IC pins (solder?). Since load removal is used for UV recovery RLD_INT will interact with the external resistances and the probable 10M of the meter to give approximately 16-17V.
    The 8 ohm load would easily overcome the RLD_INT and R2/R32 resistances of course, but the timing should not be significantly different.
  • I do not need the temperature measurement.

    From the datasheet:

    Pin 18 -> TS -> Thermistor measurement input. Connect a 10-kΩ resistor to VSS pin if the function is not used

    This is not correct then?

    Or do I need to pull down with 10k, but also pull up to VTB with 10k to get a voltage divider?

    I measured the delay of the drop to 16.2V and it is about 4 seconds.

  • I just tried to pull up with 10k, it works! Thanks for your help.

    One more question: How does the chip know if the load is removed?
    I saw that some protections require load removal to reset, which is unacceptable in an embedded application.
    Can this be changed with some external components? Or is something like plugging in a charger also adequate?
  • Hi Jesse,
    The pin 18 entry is not incorrect, but the pin 19 entry could indicate more clearly that the bias resistor is required. It is hard to know what the original author intended, but if the temperature measurement is not needed the design can use a 10k resistor in place of a more expensive 10k thermistor. I'll recommend this section be improved.
    Load removal is sensed by a comparator on the LD pin. See the bq77915 datasheet "LOAD DETECTION AND LOAD REMOVAL DETECTION" section of the electrical characteristics and the paragraph in the description "9.3.2.10 Load Detection and Load Removal Detection". Basically in figure 26 the "load detection block" has a comparator to 1.3V with the pull down switched on when there is a fault.
    If your embedded system has some method to control the pin it could determine when to move the pin and attempt to recover. If you connect LD to VSS it would recover from OCD/SCD/UV almost immediately since load would always be removed, but could not recover from OCC.
    Connecting a charger will remove the load if the charger can provide enough current to overcome the residual load of the system.
    For example if your system has a 500 uA residual load at 18V this might look like 36k ohm. The 200k RLD_INT and 470k external RLD will not provide a LD pin voltage below 1.3V. Connecting a 1A charger would overcome the 36k ohm and load removal would occur.
  • Works great. Thanks for your help. In hindsight it's pretty logical, because a 10k/10k resistor divider tricks the chip into thinking the temperature is halfway the range and thus okay.

    'Recovering immediately' meaning once the fault is cleared, the device will immediately resume operation? 

    Attaching a charger is an acceptable solution for clearing faults. You specifically say 1A in this case, how did you come up with that figure? Does a 100mA charger for example not recover the system?

    How would load detection work with low power circuits? I have some loads I want to attach that are in standby by default (~50uA) and update once every 8 seconds.

    Last question:

    In figure 29 no zener is used to limit the gate voltage (which can reach 21V (5S)). Is this because Rchg is added as some kind of resistor divider?

    I am using figure 24 in my PCB, this seems like the best option.

    Thanks in advance,

  • Hi Jesse,
    Section 9.3.2.10 of the bq77915 data sheet describes the tLD_DEG parameter which will qualify the time. "Immediately" was a poor description, but since this is 1.5 ms typical it is very quick.
    The 1A charger note was just a nominal value. As long as the charger can overcome the residual load it will cause recovery.
    The load recovery should work fine with low power circuits. The internal pull down on LD is about 200k, this would provide about 25 uA pull down at 5V and 5 uA pull down at 1V. If the 50 uA represents a residual load of the system the charger would need to provide the recovery voltage. If the 50 uA is the pulse current and residual current is lower between the pulses, if the voltage can fall sufficiently between those pulses, the system may recover by itself.
    In figure 29, RCHG is likely small with respect to RCHG2, perhaps 10k and 1M as an example. With DSG and CHG off and PACK- pulled up to PACK+ RGS were 1M the gate of the FET would see about 1/2 of the PACK- voltage, or 21/2 = 11.5V. If RGS is 3M it would see 3/4 of the voltage or about 16V. If DSG and CHG are off due to a SCD event and the cells have an inductive response which doubles the nominal voltage the gate voltage would be quite high in transient, it would be a good idea to use the zener shown in figure 24.