Section 11 of the TLC6C5912 datasheet shows a Layout Example with a large GND fill area under the device, but pin 20 is the only GND pin. Normally a large pour under the chip means there is a GND pad on the bottom of the package, but the package diagrams on pages 21-22 do not show a bottom pad.
Is the Junction-to-board Thermal Resistance just through pin 20?
Thanks,
Lee