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TPS43061: Subharmonic oscillations and inductor overheating

Mykhailo Borysov25
Prodigy 30 points
Part Number: TPS43061

Dear All,

I have built a DC/DC converter based on the TPS43061 chip. The circuit was calculated by the WEBENCH tool from the following requirements: Vin=8..16V, Vout=24V, Iout=2.3A, other settings default.

When testing the circuit, I found out that there are significant subharmonic oscillations at medium load (tested with 20 Ohm). Furthermore, the 4.7uH inductor recommended by the WEBENCH software (XAL6060-472ME by Coilcraft) heats significantly, raising concerns that it would overheat at full load. I checked the datasheet for the inductor but found that it is actually well dimensioned for the job (Isat=10.5A, Irms=8A with 20°C temperature rise). The efficiency of the converter drops below 90% when the input voltage is lowered below 15V.

Having thought that the inductor might be going into saturation, I raised the current sense resistor by a factor of 2. This did not improve things and the output voltage started to droop when the input voltage below certain level, which suggests that the inductor current is being limited.

By looking at the switching node, I found out that the regulator does not always operate in CCM. Instead, there are instances of inductor current dropping to zero clearly visible. The output voltage exhibits significant oscillations at about 1/10 of the switching frequency, depending on input voltage. With 10V input and 20 Ohm load, the observed magnitude of the oscillation was 5Vpp.

Another circuit I've built using the same chip with Vout=18..23V, Iout=3.3A but without the extra LC output filter behaves similarly (subharmonic oscillations, inductor overheating at medium loads).

My hypothesis is that the subharmonic oscillations (aka current mode instability) leads to the inductor current slowly wander between zero and the maximum set by the current sense resistor. This leads to significant Irms heating and possibly intermittent saturation. Also the inductor is heavily underutilized with respect to average current.

The question is, what would you recommend as the best course of actions? I see 3 possible reasons of the problem:

1) My board layout could be suboptimal. I used 2 layers. Even though I generally followed the recommended board layout, there are deviations in the connection of digital and analog grounds.

2) Regulator compensation network (Rcomp, Ccomp, Ccomp2) may have to be tweaked. Could anyone suggest a good starting point in compensation network tweaking?

3) The inductor may have been suboptimally selected by the WEBENCH tool. I may need a larger inductor and/or a lower switching frequency (currently ~500kHz).

Any help with the explanation or suggested course of action is highly appreciated. If anyone sees a flaw in my circuit or board layout, would be really helpful too.

  • 0
    TI__Guru* 76035 points

    Hi Mykhailo,

    Thank you for using the TPS43061. The schematic looks fine, although the 2nd stage LC filter makes the reactive load for the boost dc-dc stage and it may cause oscillation if not compensated properly. You may try to place a 1uF at C2 (currently 620pF) to kill the loop and see raise your load slowly after startup, and see if you have stable operation. If yes, then you loop compensation needs to be tuned. This is just a quick way to find out if the loop stability is an issue.

    The bigger issue that I can see is in your layout. The placements of the parts are not too bad, but the routing need to be greatly improved:

    (1) You should add two inner layers to provide better routing.
    (2) The gate drive current should flow in a short, and small loop. Please trace your low side gate driver current. Note that the VCC capacitor C3 supplies the gate drive current. You will and you will find the gate drive current flows from C3 to the IC, and from the IC LDRV pin to VT1 Gate, then passes the MOSFET to VT1 Source, then it takes a long way coming back to C3 ground pin. This current loop is not only long, but also encloses a large spatial area, introducing large parasitic inductance which affecting the MOSFET operation.
    (3) There are two reference grounds for the IC, one is PGND which is the power ground and usually is noisy due to switching of the power circuit, the other is AGND which is the analog ground for control signals and AGND should be quiet. Your current layout the AGND is a long trace but not a copper polygon, and this thin trace is not adequate to have all control signals to reference to the same voltage potential. If you add two more layers, you will have space to create an AGND polygon. Please refer to the EVM layout example.

    Thanks,
    Youhao Xi, Applications Engineering

  • 0 in reply to Youhao Xi
    Prodigy 30 points

    Hi Youhao,

    thank you for your quick and insightful response. I will test your suggestion with the compensation capacitors tomorrow. As for the layout, it can only be improved with the next iteration of the board, which will be produced in a few weeks time.

  • 0 in reply to Mykhailo Borysov25
    TI__Guru* 76035 points
    Hi Mykhailo,

    You are welcome. If you do a new board, please reserve positions for some electrolytic capacitors on the output rail (both the first and second stages of filter capacitors) to help damp out the possible high Q factor the LC filter. Otherwise the loop will be hard to close for stability.

    Thanks,
    Youhao
  • 0 in reply to Youhao Xi
    Prodigy 30 points
    Hi Youhao,

    thanks again for the good advice. It was really helpful. When I soldered a 1uF capacitor in parallel to C2, the problem went away. I have no subharmonic oscillations anymore, the inductor heating has gone down, the switching node indicates a proper CCM operation, as desired. The efficiency has gone up: now I have 92.5% with 10V input and 94.5% with 15V input.

    Perhaps the layout optimization will reduce the switching peaks in the circuit. I will also redesign the output LC filter to suppress the switching peaks better by using a lower L inductor or an EMI filter block for L8.

    One last question for you. Now that the loop has been dampened so much, the regulator probably got a poor load transient response. Could you recommend a course of action for loop optimization? Shall I just decrease C2 until I lose stability, or is there any good theory on this issue? I'm well familiar with general linear systems theory, so a description of what comprises the blocks in the TPS43061 loop and what is their gain would suffice. Do you know any white paper or application note on this issue?