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Original question:

TPS3850: TPS3850 - Window Watchdog Fault condition - Occured

TPS3850: TPS3850 - Watch dog timer/missing pulse detector

sivasuryan.R
Intellectual 610 points
Part Number: TPS3850
Other Parts Discussed in Thread: TPS3430, SN74LVC2G07

Hi

I need a missing pulse detector/watch dog output that will output low(0V) when the input is 0VDC or 5VDC or at input pulse outside the set frequency . Output will be high only when the input pulse is at particular set frequency.


Here is a picture of the desired output

I had tested the TPS3850 supervisory watch dog circuit and I got output toggling  as below every trst period (312ms). I dont want to toggle every Trst period and I want output that will always will be in low when the input is outside the boundary time (Outside the frequency range which I had setted using CWD, SET 0 and SET1).

Kindly suggest suitable IC for my above requirement.

Thanks and regards,

R.Sivasuryan

  • 0
    TI__Genius 12630 points
    R.Sivasuryan,

    It sounds like you do not need the voltage monitoring? And it sounds like you want the output to "latch" and remain logic low when a fault occurs until a user resets the system to release the latched output. If this is the case, I think TPS3430 is the best choice. This device is similar to TPS3850 but without the voltage monitoring. Also you can use an external buffer to create the latching functionality as described in this Tech Note:
    www.ti.com/.../snva837.pdf

    Please let me know if you need additional assistance or have more questions. The pictures did not upload so feel free to send them or any other sensitive information directly to my email: michaeldesando@ti.com

    -Michael
  • 0 in reply to Michael_DeSando
    Intellectual 610 points

    Hi Michael,

      Thanks for your valuable suggestion. But I prefer both voltage supervisory circuit along with this watch dog timer in same chip as like TPS3850. Will the TPS3850 works as like you had mentioned above (have a watch dog output latched) if I connect buffer as shown in application note ?

    Thanks in advance

    R.Sivasuryan

  • 0 in reply to sivasuryan.R
    TI__Genius 12630 points
    Yes, If you need latching voltage supervisor with watchdog, use TPS3850. You can also tie the /RESET output together with /WDO output if you want a single output for either fault condition (voltage fault or watchdog fault). Please let me know if you have any additional question. Thanks!

    -Michael
  • 0 in reply to Michael_DeSando
    Intellectual 610 points

    Hi Michael,

       Thanks for your suggestion. While connecting, TPS3850 with buffer (SN74LVC2G07) I got TRST time of 28 ms, but I connected the capacitor 0.1uF in CRST pin. For 0.1uF capacitor TRST time shall be 322mS typical.

    Also I observed WDO is latched to zero volts even when I provided WDI valid input (50 Hz). My configuration as follows

    1. SET0 = Low

    2. SET1 = high

    3. CWD = No connect

    My valid input for the above configuration is 45Hz to 454Hz.

    Kindly suggest any things need to do with TPS3850 configuration and settings. Kindly provide any application note on TPS3850 for latching WDO output if you have.

    Thanks and regards,

    R.Sivasuryan

  • 0 in reply to sivasuryan.R
    Intellectual 610 points
    Hi Michael,
    Is the TPS3430WDRCR part is compliance with ROHS ? Is the part active and will be available for next 7 years ?


    Thanks and regards,
    R.Sivasuryan
  • 0 in reply to sivasuryan.R
    TI__Genius 12630 points
    R.Sivasuryan,

    Yes TPS3430 is compliant with ROHS and although we can not make any guarantee the lifetime of the device, we don't see any foreseeable reason to stop TPS3430 production as long as the device continues to see demand. Please use the Qualification Summary link to check on the compliance of any TI device.

    www.ti.com/.../home

    just simply type on the TI part number to see the qualification summary.

    When latching the device, the capacitor on CRST should be very small (5nF or less, not less than 200pF) in order to prevent additional delay caused by the capacitor when latching and un-latching. Please follow the TechNote:
    www.ti.com/.../snva837.pdf

    This document provides the details to create a simple latching watchdog timer. In order to remove the latch, the buffer need to be disconnected from the CRST pin with an open circuit. Or the VDD power needs to be removed and powered up again to restart the device.

    Please read through the TechNote and let me know if anything is unclear or if you need additional support. Thanks!

    -Michael
  • 0 in reply to Michael_DeSando
    Intellectual 610 points
    Thanks Michael for your valuable support.