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UCC21521: UCC21521 high-side gate turn on time too long

Isee
Expert 6760 points
Part Number: UCC21521


Dear Team,

my customer is testing UCC21521 (PSPICE & Board). For UVLO at VDDA circuit they noticed that the part is taking 52-56us until high-side gate can be turned on AFTER the highside UVLO threshold (13.5V) has been triggered. Unfortuantely, during this time their transformer is getting satturated because it only receives low-side pulses. Andy thoughts/ideas?

Regards,

Andreas

  • 0
    TI__Guru**** 189401 points
    Hi Andreas,

    That is the expected delay time.

    In cases like this, it's best not to apply PWM until the chip is up and stable. Do they have some kind of Power OK signal elsewhere they could use?
  • 0 in reply to Don Dapkus
    TI__Expert 6760 points

    Hi Don,

    They are supplying the high-side via bootstrap - hence the supply voltage for high-side doesn`t come without PWM. What are your thoughts?

    Regards,

    Andreas

  • 0 in reply to Isee
    TI__Mastermind 34210 points

    Hi Andreas,

    Is it possible to supply a single short low-side pulse at startup? Depending on the value of bootstrap resistor and bootstrap capacitor, the charge time for the bootstrap supply will essentially follow the expected exponential behavior of a standard RC circuit:

    VDDA = VDDB * (1 - e ^ (-t / RBOOTCBOOT))

    So the bootstrap resistor and capacitor values should be set such that a short low-side pulse at startup will charge the bootstrap capacitor above the required UVLO threshold, with enough charge to spare to ensure the quiescent current of the high side circuitry does not reduce the supply voltage below the UVLO falling threshold for about 100µs after crossing the UVLO rising threshold:

    1.8mA * 100µs = 180nC, and ΔV = ΔQ/CBOOT

    So for example, with 12V supply, 1µF bootstrap capacitor, and 2.2Ω resistor: to cross safely over the maximum 9.2V threshold, solve for t in the exponential equation to find a pulse width of about 600ns. With 600ns charge time and 100µs delay time, a quiescent current voltage drop of around 180mV max can be expected.

    I recommend a pulse width of about 1.5 to 2 times the calculated duration, to account for variations in quiescent current, bootstrap capacitance vs. applied voltage and operating temperature, bootstrap diode voltage drop, and bootstrap loop inductance. Higher margin on the pulse width is needed when the supply voltage is close to the UVLO threshold because of the exponential charging behavior.

    Regards,