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CSD88599Q5DC: Tx for thermal design

Isao Takigasaki
Expert 3360 points
Part Number: CSD88599Q5DC

Hi,

Could you explain the difinition of Tx in the datasheet and how to use in thermal design?
The definition could not be found in the datasheet.

Best Regards, Taki

  • 0
    TI__Mastermind 38300 points
    Hello Taki-san,
    Excellent question. The SOA curve is shown in Figure 3 on page 6 of the CSD88599Q5DC datasheet. The horizontal Tx line, shown in red, is used to determine the maximum current to keep the device within the SOA if the case and board temperature for the power block are known. A detailed explanation and design example can be found on page 13 of the datasheet. Please review and let me know if you need any further assistance.
  • 0 in reply to John Wallace1
    TI__Mastermind 38300 points
    Hi,
    Just following up to make sure this was resolved to your satisfaction.
  • 0 in reply to John Wallace1
    TI__Expert 3360 points

    Hi,
    Thank you for your answer.

    My customer and I understand how to use Tx to get the maximum current at point of view of SOA. 

    We want to konw the definition of Tx and the reason why we can get the maximum current with using the graph, but not how to get.
    Could you explain the 2 points? 

    Your cooperation will be appleciated.
    Best Regards, Taki

     

  • 0 in reply to Isao Takigasaki
    TI__Mastermind 38300 points
    Hi Taki san,
    I am off for the holidays and will get back to you when I'm in the office on January 2nd.
  • 0 in reply to John Wallace1
    TI__Mastermind 38300 points
    Taki san,
    I discussed your questions with my colleagues since I was not involved in the derivation of the SOA curve with Tx line provided in the datasheet. The SOA curve with Tx line incorporates power loss and thermal impedance to provide a simplified graphical method to solve for maximum current capability of the power block device. It incorporates the ability to solve thermal problems where heat is drawn out through the PCB and the top of the case. As such, it is only applicable to TI devices in dual cool packages and is related to the ratio of thermal impedance thru the top and bottom paths for heat removal. I do not have a more detailed explanation or derivation beyond this.