Other Parts Discussed in Thread: PMP11047
Hello,
I'm evaluating the solution proposed in the file:
tidrdz3.pdf
PMP11047_REVA.SchDoc
My costraint is an input voltage of 18 - 56 VDC, instead of the input of 18 - 48 VDC proposed by the application displayed in the file.
My question is if I can use this schematic with the max input voltage of 56 VDC instead of 48 VDC.
Thank you.
Maurizio
