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TPS65150: Fault delay function question

WU YISYUAN
Expert 2165 points
Part Number: TPS65150

Hi,

   At Fault delay function I have some question.

   As below pic, it's VGH startup time about 200mS.

   Does it mean that if one or more voltage rise times of AVDD, VGL and VGH exceed the delay time of fdly capacitor settings,

   there is only a probability that the chip latch will occur instead of 100%?

   Why is it not 100% latch status?

  

thanks.

  • 0
    TI__Expert 6330 points
    Hi,

    I have notified our expert regarding this topic. Please expect a response by 12/21/18.

    Thanks,
    Aaron
  • 0
    TI__Mastermind 18550 points
    Hello,
    FDLY is is the time delay from when any of the rails (AVDD, VGH, VGL) is out of regulation to when chips shuts down all the rails. So if any of the rails is out of regulation for shorter than FDLY time, TPS65150 will not shutdown and continue to operate normally but if any of the rails is out of regulation for longer than FDLY time, TPS65150 will shutdown and input power supply cycling will be needed to clear this fault condition. FDLY time is also applicable during startup so during startup, if all of the rails (AVDD, VGL, VGH) are not up to their set voltage levels before FDLY time expires, TPS65150 will shutdown and a power cycle will be need to clear this condition.
    I hope this clarifies and answers your question.
    Kind Regards,
    Liaqat