UCC27714: circuit design

chentsu chung

Mastermind 6180 points

Part Number: UCC27714
Other Parts Discussed in Thread: UCC27712

Hi,

Here are some question about the circuit design of UCC27714:

1. How many MOSFET can UCC27714 drive? If now I want to drive 4 high-side MOSFET, the Ciss=10n, Vbt=11V,

and the driving current will be 1A(4A/4) per MOSFET, so I will know the charging time will be 10n*11V/1A=110ns.

If operating frequency is 300KHz, then 110ns is about 3% duty, not a good design. But the duty will be less than 1% if the frequency is 10KHz, good design.

Am I right?

2. Or is there any better way to know how many MOSFET it can drive?

3. What value of Cboot I should use? At least highier then 4*Qg/Vboot+4*Cgate(noise filter)?

4. What size of Rboot I should use? I know the peak current of Rboot is (VDD-Vf)/Rboot when first time charging, but it's only the peak current for a short time.

How to calculate the average powerloss for risistor size selection?

Could you please hlpe to answer question by question? Thank you very much!

Best Regards,

C.T.

over 6 years ago

0 Mateo Begue over 6 years ago

TI__Intellectual 2805 points

Hello Chentsu,

I have contacted the appropriate engineer to help you with your post

Regards,
Mateo

0 Don Dapkus over 6 years ago in reply to Mateo Begue

TI__Guru**** 189401 points

Hi Chentsu,

I apologize for the delay. Our team is on holiday. We will get back to you by Jan 4th.

0 Richard Herring over 6 years ago

TI__Mastermind 23215 points

Hello CT,

Thank you for the interest in the UCC27714, I am supporting this device and will work to address your questions.

For the first question: one of the considerations is the gate drive power which you calculate using the Qg, total gate charge of the Mosfets. This includes the Crss as well as Ciss. Also the switching frequency and gate resistor value is important to determine the power dissipation in the driver.

Refer to the UCC27712 datasheet, section 8.2.2 which provides guidance on calculating the gate driver power dissipation, including effect of the gate resistor value.

Can you confirm if the 10nf is the Ciss of one Mosfet or the total of all 4 Mosfets? This will make a big difference.

Assuming the 10nF is the total effective gate capacitance (of all Mosfets), the driver capacitive load is the same for HO and LO, the total gate drive power dissipation will be:

Pq1,q2=2 x VDD x VDD x Ciss x Fsw. For 300khz this will be 864mW. For 10kHz this will be 28.8mW, so switching frequency is an important consideration. There is also power dissipation from the quiescent current, and level shifter, but the gate drive power dissipation will dominate the losses in most applications. The additional losses are also explained in the datasheet detail design procedure. If there is a gate resistor, the power will be split between the gate resistors and the driver.

For the rise and fall times: if the total effective capacitance for each FET is 10nF, the number you mention of 110ns is correct for the total rise time. Here also, I would suggest you determine the Qg, total gate charge, from the MOSFET datasheet, and convert that to the total effective capacitance. Also the FET will likely be at low Rdson at a voltage lower than 11V, which can be confirmed from the Rdson Vs Vgs curve.

For example: FET Qg is 100nC at 10V, this is 10nF total effective capacitance, Rdson curve is flat > 8V. the rise time in this case will be ~80ns until the FET can conduct.

For question 3 , the total FET gate charge, switching frequency and VDD are important to know. I would refer to the UCC27712 datasheet Section 8.2.2.2 equations 1 and 2.

For question 4: a typical expected Rboot range is 2.2 to 10 Ohms, but the details on selecting a value are in section 8.2.2.4 of the UCC27712 datasheet.

Let us know if this answers your question by selecting the green button on the post.

Regards,

Richard Herring

0 chentsu chung over 6 years ago in reply to Richard Herring

Mastermind 6180 points

Hi Richard,

Thanks for your explanation in detail.

Here are some further question, could you please help to answer it question by question? this will makes me understand quickly, thank you so much!!

1. Refer to section 8.2.2.2 of UCC27712 and UCC27714, the way to calculate Cboot is different. One is calcuate by deltaVboot and times 2, and another one is using Vqg and times 10, which one you recommend?

2. Refer to section 8.2.2.2 of UCC27712, the Cboot calculate by deltaVboot(0.5V), what % of Vqg should be used as deltaVboot?

3. How you calculate"Pq1,q2=2 x VDD x VDD x Ciss x Fsw. For 300khz this will be 864mW"? 4 MOSFET*1/2*VDD^2*Ciss*Fsw?
10nF should be 1 MOSFET, but you assuming 10nF is the total effective gate capacitance previous.

4. For the 4 paralleled bridge driving, I can just times 4 of the Qtotal that calculated in section 8.2.2.2?

5. "For example: FET Qg is 100nC at 10V, this is 10nF total effective capacitance, Rdson curve is flat > 8V. the rise time in this case will be ~80ns until the FET can conduct." , is this you mean a 4A gate driver and use 1A for each MOSFET?

6. For the power dissipation like 1/2*Ciss*Vqg^2 is exist but it's not about driving current, I'd like to know is the relationship between gate driver driving current and how many MOSFET it can drive. I know there are many parameter important, but what I want to know is how to choose a gate driver for design 2A? 4A? 6A? or only the duty to consider about like question5?

Thank you very much,
C.T.

0 Richard Herring over 6 years ago in reply to chentsu chung

TI__Mastermind 23215 points

Hello C.T.
For question 1: I prefer using the method shown in the UCC27712 datasheet, which was released later, simply because you can specify the amount of voltage drop from the charging of the MOSFET gate charge. Both methods work, and is based on voltage drop of the HB capacitor from charging the MOSFET. The UCC27714 suggested method will result in a 10% drop in HB voltage specified by the 10x ratio, which is this case will be 1.14V.

For question 2: the delta Vboot used in the equation is the 0.5V which is a specific target voltage drop. The % of drop will depend on the VHB level determined by the VDD voltage and the boot diode Vf drop. Keep in mind, most MOSFET Qg numbers are specified at 10V Vgs, but this is will still give a good value estimation for Cboot even if the Vgs is a little different in the application.

For question 3: if the 10nf is for one Mosfet, than in the case of 10nF x 4 Mosfets the gate drive loss will be the 4x ratio. I suggest using the Qg specification of the Mosfets for the gate drive loss calculation, and the gate resistance.

For question 4: the gate drive power dissipation in each driver will be determined by the total gate charge, operating frequency and the 2x factor in the equation accounts for the 2 driver channels in the driver. If you have a full bridge, and I assume two drivers, the power dissipation in each driver is the same as outlined in the Detailed Design Procedure, but you will have 2 drivers with these gate drive losses.

Question 5: Yes, in this case I was assuming 1A drive capability to each MOSFET, as you had in your original example, and the 4A gate driver capability shared into the 4 parallel MOSFETs.

Question 6: For the general question on how many MOSFETs can the driver accommodate, and suggested driving current. This is very specific to the application, and our advice is still in the areas highlighted. The 1st consideration is the power dissipation in the driver since you need to determine if there will be any thermal concerns, the power dissipation is very much dependent on the converter operating frequency, and not so much on the driver gate drive current. driver power dissipation and the thermal resistance of the driver shown in the Thermal Metrics Table should be reviewed. The second, as you have inquired, is the gate drive current and the resulting switching rise and fall times. The impact on delay time relative to duty cycle, is dependent on switching frequency again. For low frequency applications the rise and fall times are not so critical, at higher switching frequency this is more of a concern. The controller will compensate for the delay of the device switching during normal operation, a consideration however is the delay time in a short circuit condition (peak current limit). The turn off delay time from the Vgs fall time may be a consideration if operating at high frequency.

I hope this helps answer your questions, please confirm on the thread.
Regards,
Richard Herring

0 chentsu chung over 6 years ago in reply to Richard Herring

Mastermind 6180 points

Hi Richard,

Thank you so much, discuss with you is worth a month's study of books.

Best regards,
C.T.

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UCC27714: circuit design