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TPS65218: Can I connect AM437X Pin G22 WARMRSTn to GPIO3 of TPS65218 as a DCDC1 and DCDC2 reset signal like we can do this for AM335x CPU ?

Part Number: TPS65218

My intention is :when CPU warm reset events like watchdog timeout or something else is happen, the WARMRSTn signal will assert, use this signal to reset DCDC1 and DCDC2.

If can't do this, would you tell me why? and why we can do this on CPU AM335X?

Thanks

Kelvin

  • Kelvin,

    I support the TPS65218 (TPS65218D0) PMIC, and from the PMIC side the answer is yes. The default value of "DC12_RST" bit in the TPS65218 Register Map is 1b, which means GPIO3 is configured as an input that will cause a Warm Reset on DCDC1 and DCDC2 and return these DC-DC converters to the original output voltage of 1.1V

    I need to re-assign this question to the AM437x processor team to answer the question from the processor side of the system.
  • Thanks Brian!

    In the document of  "slvuaa9a", it says only AM335x has this support, but I am using AM437X CPU in my new project, that is why I have this question.

  • Short answer: With AM437x you don't need the warm reset output to be connected to the GPIO3 input of the TPS65218.

    AM335x boots up with OPP100 frequencies and therefore requires DCDC1/2 voltage that corresponds to the OPP100 setting. If AM335x enters OPP50 and receives a warm reset while in OPP50, it is a violation of the device spec if the device attempts boot after warm reset with OPP50 voltage. Having the capability to handshake with the TPS65218 PMIC and resetting the voltage to default i.e. OPP100 resolves this issue. This functionality is enabled with TPS65218 by connecting AM335x warm reset output to the GPIO3 of the TPS65218 as shown in the application note

    With AM437x, the boot up occurs at OPP50 frequencies and therefore the PMIC does not require to have the warm reset output from AM437x connected to GPIO3
  • Thanks and Merry Christmas to you all!