TPS63000: VOUT not stabilizing at desired level

Hello Stephen,

I cannot find anything suspicious on the schematic (although I would recommend having an RC filter network on VINA, but it is ok to connect it directly as well). Which signal are you applying at RF_SHDN?
I would want to have a look at the layout as well.

In addition, please check the following points:
- Output capacitor DC Bias. At the output voltage, the output capacitor should still have a 15uF capacitance. If this is not the case, please add a second one.
- Inductor current capability
- What happens with the output voltage if the load is disconnected?

Hi Brigitte,

Thanks so much for your assistance.

Here is our layout, and you can see the output cap in upper left corner:

- We are currently in the process of adding more capacitance at the output.

- I think that the inductor is the issue. We were using a replacement inductor with almost no current rating.

Please give your thoughts on the layout, and I'll let you know when we have this resolved.

Hello Stephen,

Thank you for the layout. Is it correct that the VIN cap is directly below the IC and in the picture cut? The connection of VIN pin to VIN capacitor should be as good as the connection from VOUT pin to VOUT cap (VOUT is VREAD2 in the layout, correct?).

Another possible root cause could be that you connect AVIN to VIN between the input capacitor and the VIN pin. This means that AVIN will see relative high noise as the full output current is passing this connection.