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UCC24612: UCC24612 with UCC28780

user5781628
Intellectual 970 points
Part Number: UCC24612
Other Parts Discussed in Thread: UCC28780,

Hi,

I use UCC24612 with UCC28780 for an adapter design.

In UCC24612 datasheet, it say UCC24612 will use 70% of previous switching cycle.s SR off time as the minimum off time.

In UCC28780 there are ABM mode and LPM mode.

In LPM, there are 2pulses in a burst preriod, so the off time of the second pulse is too long due to enters into burst off time.

So for the new burst mode, the second SR driver signal couldn't be sent out due to the long off time of the first SR driver.

There is the same issue for ABM mode.

It looks it is the inherent issue of UCC24612 when it is cooperation with UCC28780. Right?

BR

  • 0
    TI__Mastermind 40520 points
    Hello Eleven,

    I am familiar with this issue from a previous posting of yours concerning a 2-pulse burst with the second SR pulse missing.
    The reply to that mentions these limitations that you describe above.

    However, we have since found that there is more to the story than that, but it is complicated to explain.
    We do believe that your system has entered a mode where the internal minimum off-time has been set to a time that is longer than the actual SR off-time that you are getting during the burst. We believe that sometime much earlier than shown on the scope capture the SR falsely triggered on one of the DCM ringing pulses (maybe just at the moment of transition into this 2-pulse burst pattern, before the steady-state was established). The DCM rejection function of the controller then clocked in a minimum off-time of 2xTdcm (twice the period of the DCM ring cycle). This time is now longer than the off-times of the SR (which are the on-times of the primary switch). There is not the proper condition to clear this timing, so it remains as if it is pulse skipping indefinitely.

    The way to solve this is to avoid the false DCM-ring trigger in the first place.
    One way to do this is to add a delay to the VD input to prevent the controller from sensing the very short negative-voltage interval when the ring waveform touches GND.

    I suggest to capture the moment when the SR falsely triggers on a DCM ring, probably when transitioning into the 2-pulse burst. Then add a resistor (say 1K) between the SR-FET drain and the VD input, and add a small cap (say 10pF) from VD to VS. This will add a 10ns delay to sensing Vds. Then repeat entering into the 2-pulse burst mode and increase the cap value incrementally until the SR Fet stops triggering on the DCM ring. I expect that this will then avoid any triggering on the DCM ringing, allow the minimum off-time to set to the proper level (shorter duration) and allow SR on-times for both pulses of the burst.

    I hope that you can perform this test and that it resolves your issue.

    Regards,
    Ulrich