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LM5050-1: About Figure 27 on Datasheet P18

Masazumi Ishii
Genius 3945 points
Part Number: LM5050-1
Hello

I have a question about LM5050-1.
For details, please see the attached document.

Thank you.
LM5050-1-1.pdf
  • 0
    TI__Expert 8630 points
    Hello Ishii-San,

    We are looking into this and get back in early next week.
  • 0 in reply to Lokesh Ghulyani
    TI__Expert 8630 points

    Hello Ishii-San,

    What was the voltage applied on VIN when Vext was 7.15V or more?

    If VIN < 5V, separate Vext(>5V) is required for powering LM5050-1 device through Vs pin. 

    If VIN > 5V, separate Vext(>5V) is not required for powering LM5050-1 device through Vs pin.

  • 0 in reply to Lokesh Ghulyani
    Genius 3945 points
    Hello.
    thank you for your answer.

    When Vext = 7.5 V or more Vin has 2 patterns.

    1 Vin = 5 V
    2 Vin = 3.3 V

    Both 1 and 2 are not working.

    Thank you.
  • 0 in reply to Masazumi Ishii
    TI__Expert 8630 points
    Hello Ishii-San,

    Can you let us know the voltage at Gate, Drain(OUT) and Source(IN) of the MOSFET (Q1) and the current through the MOSFET (IN to OUT) when MOSFET is not turning Off

    Vext = 7.5V, VIN= 5V
    Vext = 7.5V, VIN=3.3V

    Is the OFF pin made high to turn-off the MOSFET? What was the voltage level at OFF pin to turn-off the MOSFET?
  • 0 in reply to Lokesh Ghulyani
    Genius 3945 points

    Hello.

    thank you for your answer.

    Measured under the following conditions.

    Vext = 7.5 V, VIN = 3.3 V

    Details are in the attached document.

    When DC Vin side is OFF,

    Q1 is ON.

    Thank you.

    LM5050-1-3.pdf

  • 0 in reply to Masazumi Ishii
    TI__Expert 8630 points

    Hello Ishii-San,

    Please find reply below for the observations that you shared in previous post.  LM5050-1 will turn-off the MOSFET when OFF pin is made high or when voltage drop across IN and OUT (IN<OUT)  pins goes below VSD(REV) . You can refer to section 7.4.1section 7.3.1, Figure 1 and Figure 2  in datasheet of LM5050-1.

     

    conditions

     

     

    Gate – GND

    Drain – GND

    Source – GND

    Current (IN to OUT)

    Comment

     

     

    Vext=6.5V

    ①DC power supply=3.3V ON

    6.87

     

    3.32

    3.34

    5

    Q1 of 1 and 2 are ON since [VSOURCE - VDRAIN ] > 0 and MOSFETs are in forward conduction

     

     

    ②DC power supply=3.3V ON

     

    6.88

    3.31

    3.33

    5

     

    Vext=6.5V

     

     

     

    ①DC power supply=3.3V ON

     

    10.7

    3.27

    3.29

    10

    Q1 of 1 is ON since [VSOURCE - VDRAIN ] > 0 and MOSFET is in forward conduction

     

     

    ②DC power supply=3.3V OFF

     

    0

    3.13

    0

    0

    Q1 of 2 is OFF since [VSOURCE - VDRAIN ] < VSD(REV) and LM505-1 turns-off the MOSFET

     

    Vext=7.5V

     

     

    ①DC power supply=3.3V ON

     

    13.4

    3.27

    3.29

    10

    Q1 of 1 is ON since [VSOURCE - VDRAIN ] > 0 and MOSFET is in forward conduction

     

     

    ②DC power supply=3.3V ON

     

    13.4

    3.13

    3.13

    0

    Q1 of 2 is ON since [VSOURCE - VDRAIN ] = 0 and MOSFET does not go in reverse conduction.
  • 0 in reply to Lokesh Ghulyani
    Genius 3945 points
    Hello,

    thank you for your answer.

    I have an additional question.

    The circuit described last time is measured using the EVM of LM5050-1 with the measuring instrument, power supply etc. attached to the periphery.
    In the same environment
    Vin = 3.3 V common
    When Vext = 6.5 V: Source (IN) - GND = falls to 0 V and Gate - GND = 0 V,
    When Vext = 7.5 V: Source (IN) - GND = 3.13 V Gate - GND = 3.13 V, Maintained Gate = ON (13.4 V)

    Why is the supply of Vin turned off, does Source (IN) - GND = 3.13 V come out?
    There is a difference in gate voltage depending on the voltage difference of Vext.
    When Vext = 6.5, [VSOURCE - VDRAIN] <VSD (REV) is reached
    When Vext = 7.5, [VSOURCE - VDRAIN]> VSD (REV) is set. (Voltage on Vin side does not fall)
    Can you think of this possibility?
    Is there any possibility of other causes?
    Are there countermeasures?

    Thank you.
  • 0 in reply to Masazumi Ishii
    TI__Expert 8630 points

    Hello Ishii-San,

    LM5050-1 also regulates the voltage drop across MOSFET in forward conduction to 22mV (typical). If the voltage across MOSFET (VSD) goes more than 22mV, the gate voltage is increased (up-to max VGS of 12V) and the voltage across MOSFET (VSD) goes less than 22mV, the gate voltage is decreased . This is described in section 7.3.1 on Page 12 in the datasheet of LM5050-1

     

    Why is the supply of Vin turned off, does Source (IN) - GND = 3.13 V come out?

    This can be due to leakage in to IN and OUT pins when Vs pin is powered. Please refer to NOTE on Page 11 in the datasheet of LM5050-1

  • 0 in reply to Lokesh Ghulyani
    Genius 3945 points
    Hello.

    Thank you for answering.

    There is a leak at IN and OUT, and there is a possibility of lifting voltage.

    OK.

    We are currently verifying with TI EVM.
    Datasheet P19
    8.2.4 Reverse Input Voltage Protection With IQ Reduction
    As for the method to suppress the leak to the GND side, I think.

    Is there a way to prevent leaks to In and OUT side?
    I think that if a short key diode is put in IN, OUT, a voltage difference will occur.

    Thank you.
  • 0 in reply to Masazumi Ishii
    TI__Expert 8630 points

    Hello Ishii-San,

    there is a way to reduce this leakage in OUT/IN pins. This can be done by turning off Vs supply with a PNP transistor and MOSFET. This is shown in attached design report.

    In the attached design(PMP20096), 1581.PMP20096_LIQ_REVA_TEST_BJT.pdf Vs is turned off by transistor Q2 and MOSFET Q4 by an external signal at TP7.