UCC28950: How to decide delay time and how to work in CS, ADEL and ADELEF of UCC28950

Please refer to below attachment.

How to decide delay time and how to work in CS, ADEL and ADELEF of UCC28950.xlsx

Hello User

The adaptive delays set by the resistors at the ADEL and ADELEF pins use an average version of the CS signal to determine the extent to which the delay is modified, there is an internal RC filter in the IC that does this. This means that the delay will be function of the duty cycle - as you have observed. It will also be a function of the switching frequency

Regards
Colin

Dear Colin

Thank you so much for your answer.

I have new questions.

What is "an average version of the CS signal"?
Is this Vrms of the CS signal?
If KA is 0.5 (RA and RAEFHI are same value), ADEL pin check 0.3V when Vrms of CS pin is 0.6V.
Is this right?

Would you help us to explain the internal circuit details of ADEL and ADELEF?
(we can find the internal RC filter of CS pin at Figure 38. DCM Function on datasheet.
We want to see the internal circuit of ADEL and ADELEF.)

Thank you and Best regards

hello User

The signal at the ADEL and ADELEF pins is passed through an internal filter and this is used to generate a current proportional to the average value of the voltage at the pin. This is then used to modify the delay programmed by the resistor at the DELAB, DELCD and DELEF pins according tho the characteristics shown in the data sheet.

I'm afraid I cannot share the internal circuitry of the ADEL / ADELEF pins without a Non Disclosure Agreement in place. Please contact your local TI office or FAE engineer if you wish to pursue this further.

The internal circuit is a simple averaging filter. An RMS calculation would be more complex to implement.

You are correct - if KA is 0.5 then the ADEL pin would be at 0.3V when the CS pin is at 0.6V.

Most applications for the PSFB run at a constant input/output conversion ratio so the duty cycle is more or less constant.

Regards

Colin

Dear Colin,

Thank you for your strong support.

I will contact local TI FAE.

Sorry, I have a question.
Is the signal at the CS pin used to generate a current proportional to the average value of the voltage at the pin also?
or to the peak value of the voltage?

(I understood CS have an internal filter, I want to know how to check the voltage for delay time at CS.
mean, after through an internal filter, Which point does CS detector of inside of IC check? the waveform of the peak value? or the average value?)

Thank you and Best regards

Hello User

As noted in  section 7.3.14 in the Data Sheet, the signal at the CS pin is fed through a 30ns time constant to provide some leading edge blanking and is then added to the RAMP signal (for slope compensation) and then sent to the PWM and Cycle-by-Cycle comparators. There is no filtering applied to the CS signal so that the comparators will trip when the peak value of the signal reaches their respective thresholds (COMP-0.85V or 2V). There is a 100ns propagation delay from the CS pin to the outputs. This means that the outputs (OUTx) will change state 100ns after the voltage at the CS pin reaches the comparator thresholds (modified to take account of the 850mV offset and the slope compensation ramp of course).

The block diagram in Figure 36 is a good representation of the system.

Regards

Colin