TPS54531: BUCK DESIGN

Hi Monisha,
The output cap is too small, making the loop unstable.
You can use webench to change the output cap and get the recommended compensation value, here is the link I created for your schematic.
webench.ti.com/.../SDP.cgi

Hi Monisha,
It's not good when the phase margin is smaller than 35deg, because
1. the output will have ring at load transient.
2. SW jitter will be big, resulting bigger output ripple.
3. IC parameter varies from device to device, It will cause potential risk.
Suggest you click "Apply" to my shared link, and change the R30, C19, C22 value.

Hi Monisha,
The capacitor derating should be considered. That's why I put 2.3 uF rather than the original 4.7uF, for rough estimation. Contact your capacitor supplier for detail explanation.

Hi Monisha,
You mean you want to replace the two 4.7uF to one 10uF? I think it's fine, the loop won't change too much. But if you want to double confirm, you need to know the derated value of the 10uF at 5V and use webench to double check. You can read capacitor datasheet or ask capacitor vendor for the derated value