TPS51220A: Solder void from pin to pattern

Nariaki Ogasawara

Part Number: TPS51220A

Hi team,

This is general question about surface mount.
The customer is using TPS51220A, they are investigating the failure mechanism.
They want to know below information.
Is there the definition of solder about void density from pin to pattern?
There should be no voids of no more than % of the area in the mounting area of the soldered portion?

Regards,
Ogasawara

over 6 years ago

0 Edwin Zang over 6 years ago

TI__Expert 6425 points

Hi Ogasawara,

I'm sorry for confusion about your question.

What do you mean "pattern"? Can you give more detail of your question?

BRs,

Edwin.

0 Nariaki Ogasawara over 6 years ago in reply to Edwin Zang

TI__Intellectual 1215 points

Hi Edwin,

The pattern is foot print of board.
If the solder void density is huge, the resistance between device pin and board would be increase.
e.g. The contact resistance of the DRVH 1 increases and there is a possibility that the high side FET and the low side FET are simultaneously turned on due to the high side OFF delay.
Is there the spec or guide about the solder void density?

Regards,
Ogasawara

0 Edwin Zang over 6 years ago in reply to Nariaki Ogasawara

TI__Expert 6425 points

Hi Ogasawara,

Normally it is recommend for the voids to be less than 30% per IPC-7093. You also can search some data about IPC-7093 to refer.

BRs,

Edwin.

0 Nariaki Ogasawara over 6 years ago in reply to Edwin Zang

TI__Intellectual 1215 points

Hi Edwin,

If the void is more than 30% per IPC-7093, what is happen TPS51220A?
Is it able to malfunction?

Regards,
Ogasawara

0 Edwin Zang over 6 years ago in reply to Nariaki Ogasawara

TI__Expert 6425 points

Hi Ogasawara,

Thermal will be worse, efficiency will be lower. I don't know whether it has other risk.

it's strongly suggested that void is more than 30%.

BRs,

Edwin.

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TPS51220A: Solder void from pin to pattern