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TPS65381A-Q1: Reading back SAFETY_CHECK_CTRL register after LBIST/ABIST

Koichiro Tashiro
Mastermind 22945 points
Part Number: TPS65381A-Q1

Hi,

My customer is using TPS65381A-Q1 + TMS570x.
He reported strange behavior when reading back SAFETY_CHECK_CTRL register in TPS65381A-Q1.

Suppose LBIST and ABIST are finished and 0x0F is written to SAFETY_CHECK_CTRL register,
then customer immediately reads back the same register to check written value.
Customer expects to read 0x0F, but 0x00 is read instead. If the register is read again a later, 0x0F is read as expected.

Please note that customer checks ABIST_RUN and LBIST_RUN bits in SAFETY_STAT_3 register before writing SAFETY_CHECK_CTRL,
and confirms both bits are 0 (means LBIST/ABIST are not running).

Is this expected? Why such case happens?

Customer notices that “Initialization source” of SAFETY_CHECK_CTRL is “NPOR, post LBIST reinitialization”.
Does this mean there is some reinitialization period after LBIST and register value cannot be read properly during this period?

Thanks and regards,
KoT

  • 0
    TI__Mastermind 20590 points

    Hi KoT,

    As noted in section 5.4.7 of the datasheet, the SPI registers are in-available while BIST (LBIST) is running.  So once if the software is running LBIST manually in DIAGNOSTIC or ACTIVE states it must wait 21 ms before attempting to write or read any register.  If the software is attempting to write (or read) any register in the first 21 ms after RESET was released the SPI is also not available assuming AUTO_BIST_DIS is cleared to 0 (default) since BIST will automatically be running then.

    So if the customer read any register during those times or attempted a write during those times it would be in-available. 

    What is meant by initialization source is what are the causes that can re-initialize the register to it's default value.  In the case of the SAFETY_CHECK_CTRL it will be re-initialized due to a device Power on Reset (NPOR) event causing the device to fully reset itself and anytime LBIST is run either on software control or on the transition from RESET to DIAGNSTIC state while AUTO_BIST_DIS is cleared to 0 (default). 

    Please check the timing of any reads and writes with respect to LBIST run time either under software control or an automatic BIST run.  Also, check the correct commands are being used and the read/writes are actually to and from the correct register and check the STAT[x] bits to make sure there are no SPI errors during the read/write.

  • 0 in reply to Scott Monroe
    TI__Mastermind 22945 points

    Hi Scott,

    I am asking customer to check LBIST timing and SPI STAT[x].
    Please wait for a while.

    Thanks and regards,
    KoT

  • 0 in reply to Scott Monroe
    TI__Mastermind 22945 points

    Hi Scott,

    Sorry for the delay.
    Customer confirmed they read SAFETY_CHECK_CTRL just after ABIST_RUN, LBIST_RUN go to 0.
    Then SPI is not accessible.
    Now adding ~21ms waits solves the issue.

    Customer is asking whether it is OK to wait until SAFETY_STAT_5.FSM[2:0] is 07h(DIGNOSTIC state) instead of just waiting 21msec.
    It seems the status changes ~21msec after BIST and customer confirmed it works on board.
    But they want to know this is aligned to device specification.

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Mastermind 20590 points

    Hi Tashiro-san,

    The datasheet explains in section 5.4.7, bullet point 3, that the LBIST run time is 4.2ms, but after the LBIST there is a 16-ms wait time as the digital filters covered by LBIST are filled.  During those times the SPI may or may not be available and the read values from a register may not be re-filled yet.  The datasheet states: "The SPI registers may be unavailable during a BIST, so no SPI reads or writes should be made while the BIST is running."


    The software should wait 21ms before making any SPI communication when BIST is running.  So the recommendation would be to wait the 21ms and then read via the SPI the SAFETY_STAT_5 FSM[2:0] to confirm the device is in DIAGNSOTIC state.

    If they do not wait the 21 ms there is some possibility that the software may read the SPI at a point in time where it might be available during BIST and read the state is DIAGNOSTIC and transition the software before the TPS65381A-Q1 has finished the BIST. 

    Best Regards,

    Scott

  • 0 in reply to Scott Monroe
    TI__Mastermind 22945 points
    Hi Scott,

    Sorry my late reply.
    I understood.

    Thanks and regards,
    Koichiro Tashiro