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BQ25895: Minimum system load current on Vsys, minimum charge current, transient load performance

Part Number: BQ25895

Hi there

I have both the evaluation board and a custom design based around the BQ25895. I have three questions that require answering:

1/ Minimum load on Vsys - On page 8 of the datasheet it specifies a "battery discharge load current (min) of 15mA". It also specifies "system discharge load current (min) of 30mA" (see image embedded in post)

  • Does this mean that Vsys will be unstable with less than 30mA of load on it? If not, what exactly does this mean. My intended system, in full shutdown could use as little as 10uA from Vsys. Is this a problem?
  • If this is the case, surely your application note on MPPT tracking will be affected since the MSP430 board will regularly use much less than this ( http://www.ti.com/lit/ug/tidudj2/tidudj2.pdf
  • On my custom board, it has shown Vsys instability with marginal power available on the input or very low loads on the output. I believe this is due to incorrect PCB layout and PMID capacitance being omiited and modified on afterwards via a poor connection.

2/ Minimum charge current - I am using a solar panel connected to Vbus and have used a MPPT routine to set VinDPM accordingly. I am able to charge the battery at very low currents (as little as 1mA, after quiescent current taken from the total available) by taking advantage of the VinDPM feature.

"Typical fast charge current regulation range" is specified as 0 - 5064mA in the datasheet.

Can you confirm that this use case and behaviour is within specification? (charging at such low currents)

3/ Transient load response on Vsys. Using the BQ25895 evaluation board with the following settings, a 3.7V battery (with 0 ohm impedance), applying a 2 ohm power resistor instantaneously (a real resistor being connected via wires) creates a Vdrop. What Vdrop, excluding cables etc. when

  • Just the battery being connected
  • Being supplemented from Vbus in with a 5V, 0.5A supply

Would it fall below the battery voltage for a short period of time, after losses (through RdsON on fet, cables etc.) when the FET's are potentially changing state?

  • Hi,

    1. The charger has internal pull down on BAT and SYS that could be controlled via I2C register REG03[7]. The discharge load current refers to this pull down current, not related to your application. PMID cap is crucial as it is the input cap.
    2.The actual charger current can be lower than minimum setting, but you need to consider the efficiency of the charging. This charge is not to deal with mA charging.
    3.The system power exceeds the input power. The charger will be in supplement mode. The voltage drop would be the I_supplement x (Rds_on of Q4 + R_battery). The battery internal impedance could not be 0 and contributes to the voltage drop on SYS.