Hello TI guys
1. As the technical manual states, the 12 bits ADC module uses successive approximation algorithm. But it's very slow. So I would like to know what kind of algorithm does the EADC use to achieve fast sampling and conversion.
2. As the technical manual states,
The EADC takes either 16 or 32 cycles of the 250 MHz high speed clock to complete an analog to digital conversion. The timing logic runs continuously, producing samples every 64 or 128 ns. This gives maximum sample rates of 16 MHz and 8 MHz respectively.
So, And what's the diffrence between 8MHz and 16MHz sample rate? Which one can get more accurate result?
Looking forward to your reply
BR
Dana
