UCD3138A: What is limiting the DPWM's minimum period(maximum switching frequency)?

The 500 ns number actually comes from the maximum speed of the compensation filter. I just wrote a little test program where I had the DPWM running at 20 MHz, and it would probably run even faster than that. But there are other issues that limit the practical use of the DPWM for power supplies at higher frequencies. Probably the biggest one is the update window, which you really want to keep moving edges out of. It's 128 nanoseconds. With some topologies, the resolution is 250 psec, which would probably permit higher frequencies, but with some, like LLC, it's 4 nanoseconds. What application do you have that you need more than 2 MHz.?