The LM5116 spec sheet says to couple a pulse thru a 100pF cap into the RT/SYNC pin with enough amplitude to raise this pin from its normal 1.215V bias to greater than 4V.
If I use a 5V logic gate to create this pulse then the RT/SYNC pin will reach a peak of 1.215 + 5 = 6.215V if the logic rise time is fast. Is there a destructive maximum voltage limit for this pin?
Does the input impedance of the RT/SYNC pin stay extremely high when the pin voltage is >1.215, such that the RT resistor is the main discharge path?
What goes up, must come down. When the 5V logic gate returns to zero, it may pull current out of the RT/SYNC pin if the 100pF coupling cap has discharged any of its voltage. Does this inherently speed up the LM5116 internal clock? I plan to use 27.4K for RT to get a free-running frequency of about 120KHz, then sync it to an external 150KHz clock. If this external clock is a square wave then the T(high) is 3.33uSec. The 2.74uSec time constant of the 100pF and 27.4K will discharge the 100pF from its 6V peak down to 1.7V from ground just before the logic goes back to zero. This would drive the RT/SYNC pin negative; any harm?
If I use a very brief logic pulse instead of a square wave (to avoid this negative drive), how much time is required for the LM5116 to detect a valid SYNC pulse?
Is there a forced dead time or a minimum On time of the PWM duty ratio if the RT/SYNC pin is held high for too long? How long is "too long"?
Thanks for your help.
