TPS54060-EP: what happens if Vin < requested/configured Vout ?

Hey Amos,

Since this is a buck controller, the controller can only step down voltages. If the input is 9 V and the output is set to 24 V, the output of the device is 9 V.

100 % duty cycle means there will be no switching and the top mosfet will simply connect the output to the input voltage.

The BOOT capacitors are not for the output, but rather the high side gate to be able to open the top mosfet.

Thanks,

Daniel

Daniel Hello,

thank's for your detailed explanation.
i knew that the BOOT capacitor is for the Gate of the TOP Mosfet, in order the Gate be higher than Source. but my doubt/question is : in case of 100% duty Cycle, this means no switching, this means DC. In DC the BOOT Capacitor will not do the work of booting the Gate voltage, so how does the top MOSFET works ? how does the Input voltage connected to Output ? maybe there is additional bypass with P-Channel to connect the Input Voltage to the Output, or there is internal charge pump that makes it possible to use the same TOP MOSFET. i wonder how it works, and will it really be able to connect the Input to Output without voltage drop (and ofcourse extra Power Dissipation).

kindly regards
amos

p.s

i apologies for digging deep inside the structure of the device. however, since i am a board designer, if i screw-up and board does not work, in our logistics it can introduce delay of 3 months, it's very painfull.

Hey Amos,

Are you planning on using the device such that you try to make the output 24 V and if the input drops below this the device outputs the input voltage?

Thanks,
Daniel

hi Daniel.
the answer to your question is yes.
in previous designs we used a buck-boost converted. it caused us problem it behaved in some strange way, maybe because there is a region where it osclilates from buck to boost and vice versa. i don't know exactly the reason, the fact is that it caused us problem in emi/rfi qualification.
in this new design, i came to a conclusion that Buck dc/dc might be enough. i just need to guarantee Vout will not exceed 24VDC. if Vin drops to 9V, than Vout 9V is acceptable. but i am worried that in this case Vout will be 7V. this is why i try to understand better the 100% duty cycle feature.

kindly regards
amos

Hey Amos,

To alleviate worry on why the nMos will stay on during 100% duty cycle I will say this:

To first turn the top fet on at start up there is circuitry there to handle that. Its usually good for a couple of switches, but eventually the actual switching will take over.
This circuitry will sometimes take over and apply the "100%" duty cycle, but the more common way for it to happen will be because initially the duty cycle will increase to 100%.

As the duty cycle increases to 100% the device is switching and the bootstrap will allow the voltage at the gate to get high enough. When the device gets to 100% duty cycle the top FET gate will be held high and not discharged keeping the top FET open.
During 100% duty cycle the top FET will stay open and the device will act similar to an LDO with a drop out determined by the output current and the RDSon of the top FET.

Either way the top FET has a way to stay open and cause the 100% duty cycle.

Thanks,
Daniel