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BQ76930: I2C PROTOCOL & CRC

Tomas Coggio
Prodigy 40 points
Part Number: BQ76930
Other Parts Discussed in Thread: BQ76940, , MSP430G2553

HI 

I am trying to debug a 7S Battery pack which is using the BQ7693003. I don't have an EVM only an I2C analyser.

When I read the I2c on startup, I get this. The problem is the CHG and the DSG pins are both zero, thus no drive to the LoSide FET.

I'm a little confused as to the Protocol (as per below and would like some help to analyse to see if I can get a clue to what is going wrong)

Could someone also explain the CRC methodology and how it is derived in one of these.

Thanks 

Tom 

1 Setup Write to [0x08] + ACK
I2C Write
 
2 0x0B + ACK reg B ?  
3 0x19 + ACK DATA ?  
4 0x7A + ACK     CRC ?  
5 Setup Write to [0x08] + ACK SLAVE ADDRESS ?
6 0x0B + ACK REG B ?  
7 Setup Read to [0x08] + ACK ?  
8 0x19 + ACK ?  
9 0x0D + NAK     put slave in idle?
10 Setup Write to [0x08] + ACK    
11 0x51 + ACK    
ADCOFFSET
  
12 Setup Read to [0x08] + ACK SYS_STAT  
13 0x2C + ACK     ?  
14 0x86 + NAK     put slave in idle
15 Setup Write to [0x08] + ACK
Read with Repeated Start?
16 0x51 + ACK  
17 Setup Read to [0x08] + ACK  
18 0x2C + ACK  
19 0x86 + NAK        
  • 0
    TI__Guru 54715 points
    Hi Tomas,
    The analyzer is certainly helpful. In the list above you have 2 things to determine, the CRC and the protocol.
    For the CRC, see the bq76930 data sheet section 7.3.1.4, also see the application note "I2C Communication Sample Code for the bq76940 with a
    CRC Option Based on the MSP430G2553" www.ti.com/.../slva626b.pdf and its associated software found in the product folder Tools and software tab www.ti.com/.../toolssoftware
    An online CRC calculator can be handy also, select one you like with the proper polynomial as shown in the data sheet or application note. It is sometimes represented as 1 0000 0111, 0x107 or 0x07.
    Remember that when the CRC includes the device address it must be encoded as it will appear on the bus. The 7 bit address of the bq769x0 0x08 will shift left to 0x10 for a write, and add the read bit for 0x11 for a read.
    For the sequence above steps 1 through 3 would be bytes on the bus including the CRC, the device must get the right CRC or it will ignore the write: 0x10, 0x0B, 0x19, 0x7A. When entering the string into an online CRC calculator to check what the host sent most do not want the spaces, so enter 100b19 and the result is 7A
    This was the setup of the CC control register, address B to the required 0x19 value.
    The next set of bytes steps 5 through 9 reads back that value. CRC is done on the last device address and data as shown in the data sheet and apnote, to check enter 1119 and the result calculates 0x0D.
    Additional sequences can be calculated similarly. There are 2 more shown, (10-14 and 15-19) both read address 51, the ADC offset. Steps 10 and 11 set the read pointer, steps 12-14 get the data and CRC. The CRC of 0x86 checks correctly, it is not clear why the host read twice.
    To determine why the CHG and DSG are not getting turned on, search through the protocol to find the commands sent to the control register and the status before and after to determine if the host was seeing a fault and not setting the bits on or if there was an error clearing the bits.
  • 0 in reply to WM5295
    Prodigy 40 points

    Thank you for your help and explanation on this WM5295.  I will investigate all your suggestions. The polynomial CRC is the thing that threw me off as my CRC gen has allways been simple (ie xor  bytes)!