LM5069: why we need to add dv/dt start-up circuit for LM5069, while no such circuit for LM5064

Hi Bin,

The need of dv/dt circuit depends on the amount of capacitive load at the output. It is irrespective of device. So, even for LM5064 some form of dvdt startup is needed if there is huge capacitive load.
We may not need dv/dt circuit if output capacitance is low. The design calculator helps you on making the decision. Can you fill your system parameters in the tool and send me for review. The design calculator for LM5069 is available at www.ti.com/.../toolssoftware

Best Regards,
Rakesh

Hi Rakesh,

Thanks for your information; I understood the purpose for dv/dt, and we can check details by excel tool.

My early understanding was w/o dv/dt circuit, we shall have start up time related with C_timer; while we expected to have related short fault time out window for OCP issue, such as 100us, but such setting w/o dv/dt circuit shall have quite short start uo time, and damage the MOSFET. Do you think this also one reason we use dv/dt circuit?

The left open question from mine is question two, we face issue on this; and we need some guidance on this, while we cannot have it in excel file.

Btw, the video link in excel file cannoy be accessed.

B.R.
Bin

Hi Bin,

I am not sure whether I fully understood your question. Revert back if below statement does not answer you!
dvdt circuit is active only during startup and does not play any role in normal, OCP, short circuit events. The timer starts counting only when the device is either in power limit or current limit. Timer does not operate in dvdt mode.

2) can we calculate out the charge time(16uA) to balance the related large discharge current?
can you please elaborate this question.

On the video links: looks like there is a web page update and the links are broken. I will get it fixed.
you can access the videos at www.ti.com/.../support-training.html

Best Regards,
Rakesh

Hi Rakesh,

The vedio link works, thanks!

 

Back to Q1, how can timer doesn't operate in dv/dt mode? we failed to find out any hardware level setting for this.

 

As for Q2, this was related with our Power Amplify saturation test, which asks for burst signals as some duty(less than 20%) with period as 100us or so. we found out the Vgs droped from 12V to 4V during the test. Primary analysis was the discharge current to Cdvdt is closed to 0.5A(contious current of PNP transitor) once the voltage drop at Vsource beyond threshold of transitor due to load change from 0A to full load; and the charge current shall mostly from 16uA charge pump inside of LM5069 after the voltage drop is recoveried. even the charge time is longer than discharge, it hard to get balance for this.

We are wondering whether TI met similar issue before, and maybe can provide some guidance on such application, especially for the min. period time in this case.

 

Hi Bin,

Fault timer starts to operate only in fault mode i.e., current limit mode or power limit mode. The device monitors Vds and current of the FET to take decision on when to start Timer.
In dv/dt mode, you will select dv/dt capacitor in such a way that the system draws very low inrush current. so, the FET does not see any stress and the timer does not function.

For Q2:
We have never experienced similar issue. Can you share test waveforms.
Have you tried
1. without dvdt start circuit (without PNP transistor) ?
2. Adding RC filter across sense resistor like Fig 11 in www.ti.com/.../slva703.pdf

Best Regards,
Rakesh

Hi Rakesh,

Waveform and some analysis as below, pls check;

For Q1, checked with related engineer, the purpose on dv/dt start up circuit was to make sure the circuit can work even there is short in load when power up without damage to Mosfet, which means when power up with there is short in load, the mosfet can be closed in safety; do you think w/o dv/dt start up circuit, LM5069 can also archive this?

For Q2, this is not related with transient load, but with issue as cycling brust/pulse test partern. when we remove the PNP transitor, the issue gone in the same condition.

Btw, I recall there is application note for design Rsense, to improve the current monitor accuracy, could you find it for me. Thanks!

BR.

Bin

Hi Bin,

Thanks for the details.
GATE will not pull down unless there is overload or short circuit or under voltage or over voltage event. We need to check whether the device is seeing overload event when the pulsed load is applied.

Can you share
Full schematic
Layout
Filled up design calculator for LM5069. It is available at www.ti.com/.../toolssoftware


For Q1, dv/dt circuit does not provide any additional protection during "powering up into short". Without dvdt circuit, the power limiting function helps.

For Q2, when the PNP transitor is removed, is the issue GONE ?

Sorry, i did not find any application note talking about Rsense design to improve the current monitor accuracy. Can you let me know, what exactly you are looking for?


Best Regards,
Rakesh

Hi Rakesh,

The Gate was not pulled down to zero, instead, was pulled to 4V, as we can see it waveform. and our design parameters showed there is nothing abnormal in the excel checklist file provided by TI.
For Q2, once PNP was removed, the issue was gone.
We met some limits on LM5069 for the un-balance on discharge and charge current on both Cdv/dt and Ctimer. the first one was what we discussed above the current is normal; the latter one is for over current scenario; the charge current is 85uA, and discharge current is 2.5uA; so there is limit on 10us/100us cycling burst current load testing; as for Cdv/dt, the issue was also due to discharge and charge un balance.

as for the AN, I recall during my last investigation in how to improve current monitor accuracy from +/-10% to +/-3% in LM5064, there was an application note help me.

B.R.
Bin

Hi Bin,

Design calculator cannot cover these kind of events as it depends on several external factors like board layout, component parasitics etc.

Are you in touch with any TI field engineer? Can you schedule call along with him?
As requested, I would need below details.
Full schematic
Layout
Filled up design calculator for LM5069. It is available at www.ti.com/.../toolssoftware

Best Regards,
Rakesh