TPS54318: TPS54318

Hi,

Thanks for the quick reply.

1.8V is also needed for LPDDR4 apparently.

Given that this is a CM regulator, now a few years old, I was concerned that it would be stable at the kind of light-loads expected from LPDDR4 devices.

Also, I'd like to confirm that it's possible to construct the PDN entirely from ceramic decaps, to meet LPDDR4 rail tolerances (+/- 5%?), in the presence of the kind of worst-case transients expecte dfor LPDDR4, without the risk of stability problems.

Best regards,

- Bren

We don't need the special light-load modes, as we're not designing this system with battery-saving sleep modes.

Can confirm that to keep this device in FCCM at light loads, I should check that the current-ripple-ratio is sufficiently high (changing Fsw and L), to prevent pulse-skipping?

So concerning the Cout vs B/W question, I'd like to get that just right. Could you recommend an app-note or book? Also, would you recommend the use of an FRA for tuning (like the Bode 100)?

Thanks for the help!

- Bren

Brandon,

Technically it is possible to cause pulse skipping with an unusually large inductor value. The COMP pin voltage is proportional to the peak switch current. At light loads the peak switch current will be much lower for an unusually large inductor relative to a smaller (recommended) inductor. In that case the corresponding COMP pin voltage can be below the minimum switching threshold and the device will skip pulses. That is an extreme corner case. The datasheet has an inductor sizing formula with Iout in the denominator. If you specify Iout as much lower than the nominal 3 A (say 100 mA), then you will calculate one of these large inductors. I typically will not let Iout in that equation fall below 20% of the nominal 3 A.