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The schematic is basically. A few comments to consider:
(1) There should be a jumper between VCCX and Vout (8V_Out) node, which you can insert a 0 Ohm resistor. This is get the flexibility that disconnect VCCX in case needed.
(2) We also recommend to reserve a small capacitor position across R176 to prevent tripping UVLO by some line transient noise.
(3) Reserve a gate resistor position for each FET, so you can have some freedom to control the speed of the gate drive to limit the high dV/dt and EMI. Use 0 Ohm at the beginning.
(4) Consider to add an RC snubber at the switch node.
