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TPS3820: Phenomenon for Reset pin

Shunsuke Nagata
Genius 12620 points
Part Number: TPS3820
Other Parts Discussed in Thread: TPS3823, TPS3828, TPS3824

Hi,

I found unexpected phenomenon for Reset pin.

1. Reset pin doesn't set to high after Watch dog time out + Delay time.
2. After #1, Reset pin set to high with 30ms after WDT stops.

It seems that both phenomenon is unexpected from datasheet information.

I prepared document. Could you please support this? 

TPS3820_questions.xlsx

Regards,
Nagata.

  • 0
    TI__Genius 12630 points
    Nagata,

    Is there a reason why you use a pull-up resistor at /RESET output? TPS3820 is push-pull output type so please do not use a pull-up resistor. Can you confirm if the issue remains when removing the pull-up resistor?

    -Michael
  • 0 in reply to Michael_DeSando
    TI__Genius 12620 points

    Hi, Michael,

    I will check the work without pull-up resistor.
    Btw, do you have concerns about below?

    a) Once nRESET is asserted ( set to Low), How long will the device take (?ms) to deassert nRESET when the input of WDT is recovered?
     -> I guess it should be refere the tD time (25ms typ) in data sheet. Is it correct?

    b) Is it possble to happen nRESET keep to Low even if the input of WDT is recovered?

    Regards,
    Nagata.

  • 0 in reply to Shunsuke Nagata
    TI__Genius 12630 points
    Nagata,

    a) yes you are correct, the /RESET pin remains low for tD after the fault condition is removed. This is called reset delay.
    b) If the device is in the /RESET active-low condition, and a WDI signal arrives during the reset being low, the reset will remain low until the power is turned off then back on. The only device version that does not latch this way is the version A device for TPS3823A. You can also use a FET to decouple the signal or simply do not provide WDI signals while in the reset active-low condition.

    Please see section 8.3.4 of the datasheet:

    "In applications where the input to the WDI pin is active (transitioning high and low) and the TPS3820, TPS3823, TPS3824, or TPS3828 is asserting RESET, RESET is stuck at a logic low after the input voltage returns above VIT–. If the application requires that input to WDI be active when the reset signal is asserted, then either the A version of the device or a FET should be used to decouple the WDI signal. The A version does not latch the reset signal to the asserted state if a WDI pulse is received while RESET is asserted. An external FET decouples the WDI signal by disconnecting the WDI input when RESET is asserted."

    Please let me know if you have any additional questions. Thanks!

    -Michael