Power Save mode of TLC5929

Thank you for your support!

How is your situation?

We hope earlier answer.

We have questions about Power Save mode of TLC5929.

 

Is the remove condition from Power save mode only SCLK input?

Are this IC affected by the status of LAT and DATA when we want to remove Power Save mode?

Can this IC remove Power Save mode by SCLK input when LAT and DATA are HIGH?

Does this IC keep Power Save mode as long as SCLK isn't input even if LAT or DATA is HIGH?

 

Best regards,

 

Takahiro Nishizawa

Hi, Takahiro,

As you can see from the datasheet, "If the rising edge of LAT writes '0' into all bits of the output on/off data latch or any data into the control data latch with all bits of the on/off data latch being '0', the TLC5929 goes into power-save mode. The device stays in power-save mode until the next rising edge on SCLK is received."

If the device enters power save mode, it exits this mode until the next SCLK rising edge.

Please let me know if this solves your problem.
Thanks.
Regards,
Kenneth

Thank you for your answer!

Power Save mode is removed by SCLK input only regardless of the status of LAT and DATA.
Is this correct?


Are there any problem under the following condition?
we will remove the Power-Save mode by SCLK input when LAT and DATA are HIGH status.

Best regards,

Takahiro Nishizawa