CSD17308Q3: Power NFET behaves like an SCR, won't turn off

Hi Aaron,
Can you share a schematic or block diagram showing how the the FETs are used in the circuit? Are you using the FET as a high side (i.e. floating) load switch with the DRAIN as the input DC supply and SOURCE as the output to the load? For the NFET to be enhanced in the linear region of operation, the gate must be driven higher than the input voltage by at least 3V (lowest VGS where rds(on) is specified in the datasheet). If you're driving the gate with the same voltage as VIN, as soon the FET starts to turn on, the SOURCE voltage quickly rises up near the DRAIN voltage (VIN) and VGS will be near or even below VTH for the FET. Under these conditions, the FET can be in the saturation or cutoff region. Please share more details and I'll try to help resolve the problems.

Hi Aaron,
Thanks again for your interest in TI MOSFETs. Another option is to use a p-channel FET as a high side load switch. In this case, you would swap the drain and source pins and pull the gate to ground to turn on the FET. We have p-channel FET, CSD25402Q3A, in the same package with the drain and source pads swapped. You can pull down the gate of the PFET with a small NFET or NPN and pull it up thru a resistor to the source pin that is connect to VIN. Please note, this PFET is rated -20V BVDSS and +/-12V VGS.

Attached is a representation of the circuit (one of nine sub-circuits).

CSD17308Q3-SCR-behavior.tif

I think I got the schematic to attach (below).

Yes, using the NFET as a high-side load switch, drain as input power source.  To achieve the best (lowest) drain-source resistance, I went with a Vgs ON of 9V. Granted, with minimal load on the DC-DC converter it might creep up to 9.9V, but within the 10Vgs requirement.

5751.CSD17308Q3-SCR-behavior.tif

Hi Aaron,
At first glance, it looks like this circuit should work. You're applying the output of the DC-DC converter across the G-S of the FET and you have a 1k resistor to discharge the gate and turn off the FET. Have you captured any (G-S, D-S, input and output) waveforms? It seems like turn-on is working OK, right? Perhaps some interaction with the DC-DC at turn off? My guess is the gate-source is not fully discharging and the FET remains on. Without any waveforms, I'm guessing as to the cause.

Do you have any requirements on the speed of turn on and turn off? I don't see anything in the Recom datasheet. The converter certainly has some output capacitance which will affect the timing.

I would caution about running very close to the abs max VGS rating of the FET. Any overshoot on the output of the DC-DC converter could exceed abs max and damage the FET. This may occur during load transients, start up and/or shutdown. The no load output of the DC-DC looks like it can get pretty high. This is a logic level FET optimized for 5V gate drive. You're not going to get much reduction in rds(on) by driving it beyond 8V. You may want to consider a resistor divider from G-S of the FET.

Hi Aaron,
Just wanted to follow up to see if you've been able to capture any waveforms to determine why the FET is not turning off. I did a simple simulation using TINA-TI and don't see any issues as long as the FET gate-source is driven to <1V or lower. I'm also interested in how long it takes for the output of the Recom DC-DC to discharge when the input voltage is removed. Please let me know what else I can do to help.

Hello John, thanks for the follow-up.  It seems the problem may be more unique to my printed-wiring-board traces and vias, than just a CSD17308Q3 thing.

I was easily able to recreate the problem today on the bench, however it is interesting to note that first-time power-up and commanded turn-off seems to work, but then every subsequent power-up and turn-off seems to not work (Q9 NFET not turning off all the way).

 I was using a triple output power supplies (6V@5A, + - 25Vmax at 1A).  Thus I used the proper 5V in @ 62 mA for the DC-DC converter (produced 9.6V on Vgs given the added 500 ohm Rgs).  Using a 23 ohm load on the output, the ON state showed 25V Vds at 1.0A draw for the Q9 NFET.  When the DC-DC converter was commanded off (5Vin removed), the current draw on Q9 went down to 0.87A, and 1.33V was measured on the Vgs of Q9 (external passive Rds of 500 ohm).  I then put an additional 100 ohm load on the Q9 Rgs (in parallel to the existing 500 ohm), brought the Rgs total to about 84 ohms.  Then when the DC-DC converter was commanded off, the Q9 line did correctly open up (0A draw). 

We also did the same 25V supply on a separate Q13 line (also CSD17308Q3), to see if that would have the same problem as the Q9 path.  We never saw any problem with shutting down the Q13 (at 25V@1A, turned off right away once the 5Vin to the DC-DC converter was removed).

 We also changed the power supply to be the stronger 6V line (set to 6V @ ~3A).  Using about 1.5 ohms of load, we saw the Q9 path draw 2.8A from the 6V supply.  However when the DC-DC converter was commanded off (removed source 5V), the Q9 also turned right off (no problem at 6V@2.8A turn-off).

 

So in summary:

1. Never saw a problem with the Q13 path under the same conditions.
2. Saw a problem with Q9 path when at 25V@1A, with an unwanted Vgs of 1.33V.
3. Did not see a problem switching Q9 off when at 6V@2.8A.
4. Fixed the Q9 turn-off with additional Rgs of 100 ohm (84 ohm total), for the 25V@1A condition.

 

So, the problem does show itself under the full 25V and might not show a problem at less voltage.  Also with less current (25V@ say 0.5A) we did not see a switch-off problem.  Also we did not recreate the problem with another independent path (Q13).

Thus the choice of NFET might not be the (full) problem,  and it seems the Q9 path (PWA traces, vias, proximity to Q9 pads) might contribute some of the problem.  If the Q9 chip was slightly off-center, soldered-drifted towards the gate vias, that could contribute an unwanted parasitic resistance maybe?  The fact that we get 1.33V on the gate wrt source of Q9 (when DC-DC converter turned off, input power set to 25V) is a hard fact to ignore.  Looking at the PWA we have here, it does seem like Q9 is off-center toward the gate via some.  Next experiment to try: remove Q9, replace with a "tethered Q9" (using 1/2" wire extensions from PWA pads), and see if the turn-off problem goes away.

Estimated unwanted leakage resistance from drain to gate (Rdg) may be around 9 kohm, to cause 1.33V at Rgs (500 ohm), given Vds of 25V.  Less than 100 ohms of permanent passive Rgs is unacceptable, so I need to get this Rdg eliminated.

 

Typo above: and 1.33V was measured on the Vgs of Q9 (external passive Rgs of 500 ohm).

Hi Aaron,
It seems plausible that you might have a path from drain to gate. Normally, if you follow TI's recommended footprint and solder stencil opening, the part will self-center on the pads due to the surface tension of the liquid solder during reflow. When reworking devices, you need to be careful that it does not come off center. Also, excessive flux or other contaminate on the board can cause leakage, especially since the gate is a high input impedance. Let me know how your experiment works.