CSD17573Q5B: How to cool down MOSFET in a high power dc-dc design?

Hello Ravid,
Thanks for the questions and your interest in TI MOSFETs. First, let me point you to the following blog: e2e.ti.com/.../understanding-mosfet-data-sheets-part-6-thermal-impedance. Next, let's review the power loss calculation. For Pout = 160W @ 94.5% efficiency: Pin = Pout/eff = 160W/0.945 = 169.3W and Pdis = Pin - Pout = 169.3W - 160W = 9.3W. About 0.5W higher than your calculation. I have a couple of questions: (1) how are you estimating the power loss in the FETs and (2) where are you measuring the FET temperature of 77degC? TI normally measures the case temperature on the drain land on the bottom of the package. Customers will usually measure it on the PCB very close to the device or on the top of the case using an IR camera or thermocouple. Depending on where the temperature is measured, you can calculate the junction temperature as Tj = Tcase + Pdis x Rtheta(j-c). Using the datasheet value of 0.8degC/W (to the bottom of the case), I calculate Tj in your application is 77degC + 3.2W(0.8W/degC) = 79.6degC. Most of the heat is being dissipated thru the large pad on the backside of the package. Therefore, if you're measuring the temperature on the top of the case, the junction will still only be a few degrees higher than the case. For example, if I estimate 80% of the power dissipation goes thru the bottom, then the heat thru the top of the case is 0.2 x 3.2W = 0.64W. Typical thermal impedance thru the top of the case is ~15degC/W. Then Tj = 77degC + 0.64W(15degC/W) = 86.6degC.

In the CSD17573Q5B datasheet, TI specs a max power dissipation of 3.2W based on 25degC ambient and typical Rtheta(j-a) of 40degC/W. That gives approximately a maximum Tj of 150degC.

You can maximize the copper area in and around the FETs and use thermal vias in the large pad to spread heat to internal layers. Please visit this page for more useful tips: www.ti.com/.../midlevel.tsp

Lastly, most customers derate the maximum Tj (150degC) by 10 - 40 degC depending on their reliability requirements. This equates to a maximum operating Tj of 110degC to 140degC. A typical range I have seen is 115degC to 125degC maximum operating junction temperature.

Hello Ravid,
Can you share the requirements for the DC-DC converter: input voltage, output voltage, output current, switching frequency, output inductor value and maximum ambient temperature? I can run some power loss estimates. Are you using same FET for both the high side and low side?

Hi John

Thanks for the quick response!

I think I didn't explain myself very well in the previews message.. I meant that the Pin is 160W and Pout is 151.2W so efficiency is 94.5% but it is very close to your calculation.

I measured 77c on the top case of the high side MOSFET (it is about 10c higher then the low side MOSFET).

Here is my requirements for the DC-DC converter:

Input voltage - 17.5V

Input current - up to 9.5A

Output voltage - 9.5V

Output current - up to 16A

SW frequency - 500Khz (min 475Khz, max 525Khz)

Output inductor - 10uH

CSD17573Q5B is used for both high side and low side

BTW I cannot change the SW frequency.

Thanks!

Hi Ravid,
For this design, you've chosen one of our lowest rds(on) and highest gate charge FETs for both high side and low side. While this will minimize the conduction losses, it also increases the switching losses in the high side FET and gate drive losses for both FETs. I've been using our online tool (www.ti.com/.../fetpwrcalc) to run some power loss estimates and the CSD17573Q5B is not the best choice for the high side FET due to excessive switching loss. I can recommend alternative devices that will reduce the overall power loss in the FETs and most likely help to reduce the temperature of the high side FET. Can you please provide the gate drive voltage (I'm assuming 5V) and what IC you're using to drive the FETs? If you cannot share the IC part number, then please provide the pull up/pull down driver resistance for both the high side and low side drive.

Hi John
The gate drive voltage is 5V.
The pullup on resistance is 2ohm and the pulldown resistance is 0.5ohm fot both mosfets.
Thanks

Hi Ravid,
I used the online FET loss calculator and input your design requirements. With the CSD17573Q5B for both low side and high side, the estimated dissipation in the high side is around 4.5W (no wonder it gets hot!) and low side is about 0.5W. I tried a number of different options for the high side and the best option (lowest power loss) was the CSD17303Q5. I also tried several different low side parts and the best option was the CSD18512Q5B. That combination gave me the lowest overall estimated power loss for the FETs: 2.5W high side & 0.5W low side. Based on the 1k pricing, this is a higher cost solution than the original FET you were using for both high side and low side. However, I think we can tradeoff some additional power loss in the low side for a lower cost, higher rds(on) FET. Here are the FETs I would recommend (decreasing performance & cost):

High side: CSD17303Q5, CSD17305Q5A, CSD17306Q5A
Low side: CSD18512Q5B, CSD17573Q5B, CSD17576Q5A, CSD17577Q5A

The lowest cost option based on 1k pricing is the CSD17306Q5A (2.67W) & CSD17577Q5A (0.84W). Please note, there are some slight differences between the Q5, Q5A and Q5B packages. You will need to review the packaging information in the datasheet to make sure that the package you select is compatible with the existing layout. For test purposes in the lab, you should be able to place any of the packages on the existng footprint. Please review and let me know if you have questions or need any additional information

I have an incorrect part number in my last response. It should be CSD17376Q5B.

Sorry, CSD17576Q5B.

Ok great, I will try to use the mosfets you recommended.
Thanks for your support!