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UCC24612: False SR turn-on due to DCM ringing

Gerrit Barrere
Expert 1245 points
Part Number: UCC24612
Other Parts Discussed in Thread: UCC28780,

I am using a UCC28780 controller and UCC24612-1 SR controller in a flyback circuit something like the EVM for the controller.  The supply is running now, but I am seeing false SR turn-ons between controller switching bursts when the transformer and its capacitances go into their discontinuous mode (DCM) ringing state.  The false turn-ons are happening because the DCM ringing on the UCC24612 VD pin is high-Q and dips well below the UCC24612 SR turnon threshold for the prescribed 80 ns.  The false turn-on lasts for the minimum turn-on time, or 375 ns.  I see a false turn-on followed by 3-4 DCM ring cycles at 1.5 MHz, followed by another false turn-on, etc, persisting between switching bursts.  It looks to me like the UCC24612 is blanking for its maximum time and then triggering another false turn-on.

My layout is good, and the voltages seen by the UCC24612 are the same as directly at the SR FET.

Can someone recommend a way to avoid this without ruining the good efficiency of this active clamp controller?  Let me know if you need to see waveforms or anything else.

  • 0
    TI__Mastermind 40340 points
    Hello Gerrit,

    Fortunately, I was working this very issue a couple of weeks ago and came up with an "active-damping" network to suppress the DCM ringing that follows each burst. It is admittedly a brute-force method to squelch the ringing by shorting out the AUX winding after the burst ends.

    I don't have a drawing of the circuit yet, but I can use a thousand words to describe it and then get a drawing to you in a follow-on reply.
    I use a small-signal MOSFET Q1 with Vds rated higher than the max Vaux during demag time. A diode connected in series with the drain will block negative voltage during the main FET on time. A resistor pullup to VDD will drive the gate. Another small-signal MOSFET Q2 is connected with Q2-D to Q1-G in order to keep Q1 off during the burst. Q2-G is connected to the RUN signal.

    So when RUN is high (during the Burst interval), Q1 is held off. When RUN goes low immediately after the last pulse demag, Q1 is allowed to turn on. So Q1 will absorb most of the resonant energy in the switched node capacitance and damp the ringing within one cycle. The SR control can't false-trigger on it anymore.

    Some design criteria:
    A dead short will have high peak current into Q1. Most small-signal FETs can't take a high repetitive peak, so a series resistor in the drain can help limit the peak to Q1's capability. Then the resistor must be rated for the power.
    Also a "big" FET at Q1 will have high Ciss, which takes some time delay to charge up unless the gate pullup is stiff (15K ~ 33K?). But this may become an issue at lighter loads if bias power increases significantly. So the choice of Q1 can be a bit tricky to find one with low capacitance but adequate peak current rating. And the Coss of Q2 adds to the Ciss of Q1 when turning on Q1.

    Certainly, you can start with two handy 2N7000/2 FETs (or similar) to see how it works, and finesse the design after verification of effect.

    Regards,
    Ulrich
  • 0 in reply to Ulrich Goerke
    TI__Mastermind 40340 points

    Hi Gerritt,

    Here is a snapshot of the circuit from a test board schematic.  

    (I'm not sure why it came in rotated; the original file is normal.)

    I recommend to add a resistor between the diode and the drain. 

    Start with 50~100ohms, 1 Watt (probably overkill) and see where to go from there.

    Regards,
    Ulrich

  • 0 in reply to Ulrich Goerke
    Expert 1245 points
    Excellent, Ulrich, thank you again for your prompt and helpful reply. I'm going to nominate you for a Nobel Prize. :-)

    I was vaguely wondering if there was some signal which indicated the end of a burst so I could do something about that ringing energy, and here it is: RUN. I should be able to dissipate just enough of the ringing energy to prevent false turn-ons without destroying the supply efficiency too badly.

    I will mark this issue as "resolved" since I'm pretty sure this or something like it will nail my problem. Thank you again!

    Gerrit