UCC28950: Process flow for adjustable dead time and reduce current spike

Hello Satoshi-san

Please ask the customer to send me their schematic and the waveform at the CS pin of the UCC28951, I'm at colingillmor@ti.com

The UCC28951 allows the user to adjust the OUTA/OUTB and OUTC/OUTD delays as a function of the CS signal by using the Adaptive Delays feature (ADEL pin). This is explained in the data sheet and optimising the delays is an iterative process which has to be done on actual hardware. The goal of the optimisation is that the dead time is long enough to allow the switched node sufficient time to complete the ZVS transition. Note that the AB leg of the bridge normally takes longer to make this transition than the CD leg.

The amplitude of the CS spike is a function of several things:
1/ The spike will be larger if the system loses ZVS because the dv/dt rates at the switched nodes increase significantly. Loss of ZVS is more likely at light loads. The answer is to increase the amount of energy available to drive the ZVS transition by increasing the value of the shim inductor or the leakage inductance of the transformer or by reducing the stray capacitance at the switched node.
2/ The RC filter is typically 1k / 300pF but this depends on the details of the design so these values should be taken as a guide only. It is VERY important that the RC filter be placed as close as possible to the CS pin of the UCC28951 with a very low impedance connection for the capacitor to the GND pin of the controller.
3/ The location of the current sense transformer - is it in series with the power transformer or is it in the DC rail supplying the H bridge ?

I hope this helps - please feel free to use the email address above to send me customer confidential information - we never share such information of course.

Regards
Colin