LM5113: Regarding Delayed Fall time of the part mentioned

Dear Sir,

P.l. find the attchment0511.Attachment.pdf

Hello Team,

In the schematics, cathode of the Bootstrap Diode &  +Ve of the Bootstrap capacitor are connected to HB pin.

Pl. find the scopeshots attached as per your request.

Note:All shots attached are captured with respect to GND.  HS FET's Gate signal & Bootstrap capacitor +ve terminal with referenced to HS shots will be attached shortly;

Colour of signals in scope shots:

RED Colour:  HS FET's GATE

Green Colour:  Bootstrap capacitor's +ve terminal.

Blue colour:  HS Pin / HS FET's Source

Yellow: HS FET's GATE

In continuation to previous attachment:

Hi DEVARAJAN,

thanks for your update,

what is the red and yellow trace? are they both 'HS FET gate' in your description.

I notice that your bootcap is smaller than usual and there might be an issue with the charging or discharging seen in your next scope shots, LM5113 datasheet section 8.2.2.2 helps with bootstrap cap calculation

does the issue get better if  you try a 0.1uF bootcap?

Thanks,

Dear Team,

Thanks for your reply.

Red colour is HS FET's Gate signal and Yellow colour is LS FET's Gate Signal.

Initially  C0402C103J4RACTU/CAP CER 0.01uF 16V 5% 0402 X7R +/-15ppm was used as Bootstrap cap. Then it is replaced with CGA4J2X7R2A104K125AA  / CAP CER 0.1uF 100V +/-10% X7R 0805 RoHs AECQ200. But no difference observed. Wave form attached for your reference is taken with latter (0.1uF/100V).

Pl. find the HS gate & Bootstrap capacitor supply with referenced to HS pin scope shots.

While measuring HS Gate-HS pin i found no delay in the fall time & just the ringing;  I can understand it as "once HI pin becomes low HS gate is pulled down toHS pin through HOL pin". But at the same time i measured both HS pin & HS gate with referenced to GND. there again i found the delay in fall time. What it mean actually? Because if  what i mentioned in quotes is the case, then while measuring with respect to GND also there should not be any potential difference between HS gate & HS pin once HI becomes low. Right?

Note: Blue  : BOOTSTRAP capacitor wrt HS pin;   Yellow is HS gate wrt HS pin

.

Scope shot : Yellow colour : HS gate wrt HS pin & Blue colour  : Bootstrap capacitor supply wrt HS pin.

Scope shot : Yellow colour : HS gate wrt HS pin & Blue colour  : Bootstrap capacitor supply wrt HS pin.

In this waveform, as we can observe  there is no delay in Fall time. Wave form is restricted to 1uS what i configure.

scope shot 3: Blue colour: HS pin  wrt GND & Yellow colour : HS gate with respect to GND.

Here we can observe the delay of 0.5uS which is nothing but the deadtime set between HI & LI pulse.

Hi Devarajan, 

Looking through your screencaptures, I suspect that the most likely explanation of the scope shots you are seeing is that the part is correctly pulling the high-side gate output down quickly when commanded as you see in the measurement when you use a diff-probe to measure HS-Gate to HS. I suspect that in the scope capture where you plot the HS-Gate and HS signal on separate scope channels is incorrect. In particular, I suspect the two probes were not quite perfectly compensated when you did that measurement which could show the data you are seeing. If you look, the HS-Gate signal does drop by about ~4V when it is supposed to, it just does not drop to HS, but I suspect that is because of poorly compensated probes.  The HS voltage itself drops slowly because you have little load on it to pull it down. If there is no load, HS will just stay high until the low-side turns on and pulls it down which is what you are seeing.

One thing that did catch my eye is in the plot where you plot the LS-Gate on the yellow, it does not seem to fall rapidly when the low-side shuts off, instead it seems to have alot of resistance in the gate-drive path. If this is real, it will cause shoot-through when the high-side turns on and could be responsible for the high ringing seen when the high-side turns on. I would double check this and see if the low-side gate is being driven up and down quickly. However, in your first attachment, a scope capture shows the low-side gate being driven quickly, so this seems to contradict this.

Regards,

Nathan

Dear Jeffrey & Nathan,

I thank you for reply & effort taken to solve the issues.Request you to wait for few more days for my reply as the board is used for another testing.

Regards,

Devarajan

Dear Team,

Thanks for continued technical support.

As Mr. Nathan pointed out, there is no delay in Fall time of the HS Gate. It is clearly a measurement error.

  And as Mr. Jeffrey instructed i followed Pig tail method (Using Ripple TIp) while probing  both HS Gate & BS cap supply wrt HS pin. But no improvement is observed  in Ringing. So Iam planning to provide a capacitor across Bootstrap Diode to reduce ringing. Kindly suggest is that recommended?

For your kind reference, this time i tried to eliminate all measurement errors & attached captured waveforms.

Also my pulse requirement is 10nS ON time, 50nS Pulse period, 10nS Deadtime. Pl. suggest will it work with the schematics i sent you. Why because I continuously face  MOSFET heating & followed by long term failure when it is operated at configuration mentioned.    I suspect heating is due to direct short of supply to GND through both FETs. Even sometimes i  used to hear a sound from MOSFET & suspect that is due to over current flowing through FETs during short event. Is it this ringing we are specking about is responsible for that too??

And for kind notice i have requested my seniors for sharing Layout file and waiting for thier reply.

Regards,

DEVARAJAN R

Wave form 1 : HS FET gate wrt HS pin

No Delay in fall time; Configured ON time is exactly 1uS.Configured dead time is 500nS

wrt 

Scope shot 2 : Yelow : HS gate & Blue : LS gate

No Delay is observed in LS gate Turn OFF & Turn ON. Previous one may be due to Measurement error as MR. Nathan pointed out.

Scope Shot 3 :  Yellow : HS GAte; Blue is BS cap supply wrt HS pin.

What causes Ringing???

Second ringing may be due to LS Gate turning ON

Scope shot 1: Yellow is HS Gate HS pin &  Blue is LS gate wrt HS pin

Dear Nathan,

As instructed, i found no variation while interchanging probes for  HS Gate & BS cap supply wrt HS pin measuremnt. Waveform is exactly same as what i shared yesterday.

But same measuremnt i took wrt GND. I mean  HS Gate wrt GND & BS cap supply wrt GND. In this measurement while interchanging probes i could observe the variation. But ringing seems to remain same.

Regards,

Devarajan R

Scopeshot 2: Yellow is BS cap wrt GND & Blue is HS gate wrt GND. In this waveform BS cap supply is higher.

Scope shot 3 : Yellow is HS Gate wrt GND & Blue is BS cap supply wrt GND. In this waveform, Bootstarp is lower than HS gate.

Why not this variation is observed while probing wrt to HS pin. 

Hello Nathan,

To just confirm that voltage rise(over charging) of BS cap supply to 6V/ 7V is not due to measurement error i probed each signal separately with single probe and the same result.

Scope shot 1 : BS cap supply wrt to HS pin

Scopeshot2 : HS gate wrt Hs pin

Scope Shot 3 : HS Gate wrt BS cap supply.

From the last 3 scope shots, i could infer the following: (1) Before HS FET turns On , BS cap supply is at 6V (2) When LS FET turns ON, BS supply is at 7V. (3) When HS FET turns ON BS Supply is 1V below HS gate. (4) As Mr. Jeffrey pointed out, BS cap may overcharge due to parasitic inductance in the trace.

Pl. clarify (1) why 1V difference arises between HS gate & BS cap supply pin when HS FET turns ON?or is that normal? (2) Is there any solution to solve this overcharging without changing routing? (3) is this overcharging & ringing in BS cap causes heating/ failure of High FET.I mean does this turn ON both MOSFETs at same time?    

Dear Mr.Nathan,

Thanks for your reply. Overcharging issue of bootstrap capacitor  is solved by implementing your suggestion. Previous Diode (PDS4150-13) is replaced with BAT54SLT1G. Now i think ringing & overcharging of BS cap is solved. Wave form is attached fyr.

But still heating of High Side MOSFET din't get solved. As the ON time & total period of pulse is reduced, heat of Hs FET increases. What might be the cause?

In continuation to last upload:

Also i hear a ringing sound from HS GaN FET in addition to heating. What would be the cause?

Scopeshot 1: BS cap wrt GND. Hope BS cap supply is clear.

Hi Devarajan,

In general, the power dissipation of the high-side MOSFET is caused by one of the following:

1.) Conduction losses (I^2*R*D) losses where I is the current, R is the rdson of the FET, and D is the duty cycle

2.) MOSFET Qoss losses = Qoss*V*Fsw Where Qoss is the Qoss of the FETS+PCB, V is the bus voltage, and Fsw is your switching frequency.

3.) Cross conduction losses during switching: proportional to load current, bus voltage, switching frequency and inversely proportional to transition time.

4.) Possibly shoot-through losses. Should not normally occur, but could occur if both FETs are turning on at the same time.

Though you haven't told me your current, but i suspect it is low from previous discussions, so I don't expect issues from 1 or 3. The gate waveforms look like they are non-overlapping so 4 should be eliminated unless there is lots of inductance between the driver and the FETs which could cause the FETs to turn on even when the driver is trying to hold them off.

For (2), your switching frequency is low enough  (100 kHz correct?) that the Qoss of the FETs will not be large enough cause lots of heating, but what is the load connected? Does it have lots of capacitance. Typically a half-bridge has an inductor connected which has some capacitance but not too much, however you have never spoken about the load. Is it something other than an inductor? What is its capacitance?

The audible noise is probably from ripple on a ceramic capacitor. Ceramic capacitors are somewhat piezoelectric which means they deform in response to an electric field. This means that ripple voltage on the capacitor in the audible frequency range can make the capacitor flex at that frequency and can be heard. However 100 kHz is above audible range. Maybe there is another lower frequency ripple in the system somewhere?

Nathan

Hello Mr.Nathan,

Thanks for your forum support.  I calculated Losses in HS FET & observed that it is the Qoss Loss that dominates for the following configuration:

Qoss = 14.2nC (from datasheet)

Bus Voltage = 40V

Pulse period =200nS (Frequency = 5MHz).

I could understand  by reducing Voltage / Frequency, this loss can be reduced. Is there any other solution other than touching those parameters.

Output is at No-loaded condition & above is the operating configuration in which i observed heating of HS FET.

Regards,

Devarajan R

Hi Devarajan,

  I didn't realize you were trying to switch at 5 MHz. 5 MHz hard switching with a 40V bus will result in high losses and there is not much you can do about it. You can switch faster with a soft-switching topology but that requires a major change to a new topology. Regretfully, there is no way avoid dissipating the Qoss loss when hard switching.

Regards,

Nathan

Hi Devarajan,

 There should only be IL*Rdson across the high-side when it is on. If there is more than that, something is wrong. It could be a measurement issue (probe compensation again) or maybe some unknown load. Is the supply current normal?

Regards,

Nathan