• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 63 subscribers
  • Views 699 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCC256301: Cannot set burst mode threshold below ~30%

Tim Laux
Prodigy 20 points
Part Number: UCC256301

Hi all,

We are working on an approximately 400W AC-DC converter using the UCC256301. We are a couple months along, working through some of the details..

One issue we are having is setting the burst mode transition level to a reasonable percentage of the full output power. Right now, even with the top resistor of the LL/SS pin divider removed, the converter stays in burst mode until about 120W (30%).

Maybe someone can confirm if my understanding of the LL/SS pin is accurate. By my understanding,  removing the top resistor means no current can flow into the pin, meaning the burst mode threshold (BMT) is at its minimum. With the top resistor added, the LL/SS will sink the current necessary (through the top resistor) to make the voltage on LL/SS equal to VBLK. If the external divider is set so that its output voltage is less than VBLK, then the burst mode threshold will also be at a minimum. This is because, as far as I know, LL/SS can only sink current

Regarding our issue... Typically, the burst mode duty cycle might vary between 1% to 25%, or so. Once it reaches about 25%, the converter flips into continuous operation. On our converter, the burst mode duty cycle continues to increase until it reaches 100% duty cycle (AKA continuous operation).

Any ideas on why this might be the case here?

In addition, in the datasheet, the internal voltage 'AVDD' is referenced heavily but there is no mention of what the value of AVDD, and if its a variable voltage, what drives it. Any input on that?

Thanks a lot!

Tim

  • 0
    TI__Mastermind 27095 points
    Hi Tim,

    Thanks for reaching out. When depopulating the top LL/SS resistor, the burst mode threshold will be internally set to the minimum burst threshold (~0.7V). This means if the peak to peak voltage of VCR is less than 0.7V, then you will see burst mode operation. One method to reduce the burst mode threshold further is to adjust the VCR capacitance to make the peak to peak VCR voltage larger at lighter loads (make the lower VCR capacitor smaller).

    On this controller, the "duty cycle" of the burst packets will increase as you increase the output power. There is not a hard transition between burst mode and normal switching operation however.

    The AVDD voltage is an internal 7V rail that is used to power some internal circuitry inside the IC.

    Best Regards,
    Ben Lough
  • 0 in reply to Benjamin Lough
    Prodigy 20 points

    Hi Benjamin,

    Thank you for your prompt response. It's all much more clear now. In hindsight, it seems quite obvious that the voltage across the VCR pin would related to the burst mode threshold. I changed from an approximately 100:1 divider to 50:1 divider, and am now able to adjust the burst mode threshold to something reasonable.

    Interestingly, when used in conjunction with Figure 8. (optocoupler bias circuit to avoid deep saturation) from TI's SLUA836A App Note, the burst mode duty-cycle does not increase linearly with output load. The duty cycle increases from 0% to 2% load, and then switches to an approximately 90% duty cycle state, which it stays in until burst mode threshold is reached.

    That's probably something we'll just have to work through. For now, we are leaving out the Figure 8. circuit, as the performance seems to be better without it, even though it appears the optocoupler is saturated during light-load condition.

    Thank you again,

    Tim

  • 0 in reply to Tim Laux
    TI__Mastermind 27095 points
    Hi Tim,

    Thanks for the feedback. Another option we could look at is to use a zener to clamp the fast lane gain on the secondary side to avoid saturating the opto-coupler. This circuit would clamp the maximum current on the secondary side of the opto and can be used to avoid saturating the opto when at light load.

    Best Regards,
    Ben Lough