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LP87702-Q1: power good pins default behavior

Vsevolod Elantsev4
Intellectual 2810 points
Part Number: LP87702-Q1

Hi team,

My customer asks about default behavior of power good pins:

  1. What is actual default cold-start/reset behavior of PG0 and PG1 pins? From datasheet PG_CTRL read from OTP should be 0b00000010, from TRM 0b1001010.
  2. What is default reset state of PG0_CTRL and PG1_CTRL?

The customer wants to use the pins to cascade next power sequences.

Do we have an alternative variants of LP87702-Q1 with other default behavior?

  • 0
    TI__Genius 17380 points
    Hi Vsevolod,

    Generally the values in the main datasheet for "Reset" refer to the device before the OTP loads. In most cases this is before the part outputs anything since most outputs are gated by OTP load. In some devices "0xX" is used here to be more explicit. The values from the TRM are loaded during OTP load and act as the default from that point on generally.

    The TRM values are more likely what the customer is interested in (for example what they would see if they were to do an I2C read) since the datasheet reset values only persist for a few ms while OTP is being loaded into the default registers before I2C is active.

    The primary support for this device has been notified regarding the alternative version question (and if further detail is needed on the power good pins) as I am not familiar with the current plan for LP8770 releases.
  • 0
    TI__Intellectual 950 points
    Hi Vsevolod,

    PG0_CTRL and PG1_CTRL default reset states are 0b0000000. But it is not important information since OTP will be loaded immediatly when nRST goes high. OTP load takes approximately 1.2ms. You could find the default values after OTP read from the Technical Reference Manual (TRM)

    If customer wants to use PG pins to cascade power sequences, recommendation is to tied it with GPO. That way PG is low during start-up, after all rails are up, PG => high and change state from high to low during shutdown and stay low until all are OK again.

    LP87702DRHBRQ1 is only released variant at the moment. However, if customer has I2C access, they could change some OTP settings after start-up and before enabling the device (nRST = high). Only notified issue is that those settings are not permanent. If the device resets, it will load OTP default values again and all I2C changes need to be done again. It could happend following cases:

    • Software reset with SW_RESET bit in RESET register
    • NRST input signal low
    • Undervoltage lockout (UVLO) reset from VANA supply
    • Watchdog expiration (depending on watchdog settings)

    You could contact to your local sales team to verify if the business case is big enough for the custom OTP

    Thanks

    Tuomo