Hello
I'm using TPS54821 regulator in my project. I have used TI WEB BENCH Simulator and implemented my design, wherein it is showing very less ripple value. But practically I'm getting 100mV. I need ripple to be less than 50mV.
I have used two 100uF ceramic capacitors on output (1.8V@ 8A).
What other constraints that may effect voltage ripple?
What I can do to reduce voltage ripple less than 50mV?
Please help me out in this concern.
Regards
Nidhi P Shetty
Hi Nidhi,
Please upload your schematic, layout and Vout waveform for further analysis if the bellow tips doesn't work.
From schematic side, you can add more ceramic cap, specially add another 0.1uF cap to reduce high frequency noise. Use bigger inductor also helps.
From layout side, put Cin close to IC. Rotate inductor direction to see whether the high frequency noise reducers.
From the test method side, use 20MHz bandwidth limit, put the probe exactly across the output cap, use small GND wire:
