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LM5069: PGD pin real operation

Brice Barottin
Prodigy 60 points
Part Number: LM5069

Hi,

I'm using the LM5069 with a PSMN3R8-100BS as the MOSN Switch to
have the Hot-Swap function, and the soft-start when I enable it via a little MOS (µC controlled) on the UVLO Pin,
as preconised in the LM5069 datasheet.

In my desing the PGD pin is pulled high with a 47K resistor going to the VOUT (OUT of the LM5069, a 48V bus).
After several tests and modifications, for some reasons (Rsense modification without modifying RPWR),
the PSMN3R8-100BS died in a Drain-Source short circuit ; but without damage for downstream circuitry.

As the MOS in short circuit :

  • when the µC "shutdowns" (via the little MOS on the UVLO pin) the LM5069 and the tension (48V) it commands,
    the 48V bus does not fall effectively.
  • but the PGD signal goes down, which is (as presented in the datasheet being just a comparator between VIN (SENSE) and VOUT)
    impossible and a false information as the MOS in short circuit, the VOUT could not be 2.5V under SENSE (VIN)...

So I want to know if this is :

  • A normal behaviour (I can misunderstand the datasheet)
  •  Not mentionned in the datasheet, but in reality the PGD pin is a convolution of the comporator (SENSE-VOUT) output and the UVLO PIN
    (maybe this is not wanted)
  • My LM5069 has been damaged
  • ...

Best Regards,

Brice

  • 0
    TI__Guru** 105361 points
    Hi Brice,

    Welcome to E2E!

    Can you please fill the design calculator and send me for review. It is available at www.ti.com/.../toolssoftware

    Best Regards,
    Rakesh
  • 0 in reply to Rakesh
    Prodigy 60 points

    Hi,

    Thank you for your answer.

    I don't think this will show any problem to resolve my issue,
    as I said I discover the problem due to an error later corrected successfully.
    (And I don't know if I could send any precise information of this design).

    You can try on the eval board to see what I mean :

    • leave out the MOSFET
    • Replace it by a wire between Drain and Source (Shunt SENSE and VOUT ; GATE now HZ)

    I made it on my board.
    You will see what I observed : not touching to the power supply arriving at SENSE,
    you disable the LM5069 (and normaly the MOS connected, disabling the voltage @ OUT ; normaly)
    by shorting the UVLO pin to ground.

    As read in the datasheet, in this (abnormal) situation, PGD should stay High but it goes Low...
    For me if PGD is just related to a comparator between SENSE and OUT this sould never happen...

    Best regards,

    Brice

  • 0 in reply to Brice Barottin
    Prodigy 60 points

    Hello,

    I can send you this sheet.

    I broke up the MOS when I reduced Rs(ense) without at the same time reducing Rpwr.
    Which resulted in an excessive Plim while the MOS switched and therefore died in Short-Circuit.

    With good value of Rpwr linked correctly with Rsense and maximum MOS power dissipation, circuit
    works without any problem.

    I hope this could help you to understand.

    But my main question remain the same and not yet answered :
    "Is it normal when (abnormal situation) SENSE and VOUT short-circuited (dead MOS or wire) and UVLO pulled to ground the PGD pin goes down ?"
    For me not because in this case SENSE and VOUT remain the same and PGD is (datasheet) only attached to a comparator between SENSE and VOUT, and not linked to the UVLO in (apparently) any way.

     

    Regards,

    Brice

  • 0 in reply to Brice Barottin
    TI__Guru** 105361 points
    Hi Brice,

    Thanks for the information.

    I have verified your case on EVM --> shorted the FET and pulled UVLO to ground --> PGD pin goes down. This condition is not covered in the datasheet block diagram as it is fault case -> bypassing the hot-swap protection.

    Best Regards,
    Rakesh
  • 0 in reply to Rakesh
    Prodigy 60 points

    Hello,

    That's I was thinking. But what I want to point out is that situation makes PGD irrelevant and dangerous.
    This kind of failure (MOS dead in Short-Circuit due to over-current/power) is one of the most common for this circuit.
    Moreover, a PGD pin indicate the state of the output voltage and can be used to enable downstream devices, knowing the state of
    the power rail...

    And if there is this (for me) common failure with the LM5069 with the enable scheme on the UVLO pin,
    the PGD pin indicates the opposite of the reality (absence of voltage when UVLO disabled) which can lead
    to dangerous and maybe harmfull situtations !! ...
    When it arrived to me, I was seriously wondering what it was happening since PGD pin assured me there was no usable voltage
    and my downstream circuitry worked in a stranged downgraded mode.
    For me amongst others, PGD is to be used with confidence, here's it is impossible and dangerous.

    For me PGD pin has in this case an illogical and dangerous behaviour, and the datasheet let us guess it
    won't act like that (UVLO pin pulled down, PGD pin goes down) since only her comparator operation is described.

    So for me, this should be corrected on the IC chip for the next version planned.
    And while this is not done, this behaviour has absolutely  to be mentionned in the datasheet !!


    Regards, 

    Brice

  • 0 in reply to Brice Barottin
    TI__Guru** 105361 points
    Hi Brice,

    LM5069 block diagram can be updated to reflect the dependency of PGD on UVLO status.

    So, you wish PGD to be high when there is FET short irrespective of UVLO status - right ? How does that help in protecting your downstream circuitry? or Am I missing what you intent to do with PGD information ?

    Best Regards,
    Rakesh
  • 0 in reply to Rakesh
    Prodigy 60 points

    Hi,

    Once again, I can misunderstand...

    But to my mind, as reading the current datasheet, the PGD pin relies only on comparing Vsense and Vout.
    So in the case of the switch shorted and the UVLO pulled down, PGD should stay 'high' ; since the datasheet mentionned that
    it relied only on a comparator between Vsense and Vout.

    Do you follaw my opinion on that specific case ?

    Regards,

    Brice

  • 0 in reply to Brice Barottin
    TI__Guru** 105361 points
    Hi Brice,

    Agree on that.
    I will get it updated in the datasheet next revision.
    Thank you!

    Best Regards,
    Rakesh
  • 0 in reply to Rakesh
    Prodigy 60 points

    Hi Rakesh,

    Thank you for your answer and understanding.
    If mentionned it will be predictable and fair.

    Just one thing to understand why it would be preferable to have PGD relying only on a comparator :

    • A µC (or whatever [µC = micro controller]) commands the LM5069 to go on (via the UVLO pin) or off and the PGD pin returns to it
      as a back information
      • if everything is okay, Vout rises and PGD goes high, the downstream circuits can be supplied
        On the OFF action, Vout falls as PGD, the information back, the µC deduces that everything is in order.
      • if the MOS shorted, on the OFF action (µC on the UVLO pin), Vout doesnot fall but PGD goes down as well,
        the µC deduces that everything is okay, downstream circuits with no energy as the tension is disabled...
        But in the reality the tension is still here, maybe the downstream circuits still supplied and the dramatic failure (MOS shorted)
        cannot be seen in this way by the µC...
        That's why PGD pin is irrelevant for me in the LM5069 and (still for me) it is no sense to correlate UVLO/on-off to PGD pin...
        I will have to make an external extra circuitry to have back the information I want.
        As said, the real functionment of PGD have to be mentionned in the datasheet because it is primordial.
        Thank you very much for your patience and understanding.
        Have a nice day,
        Brice