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TPS563200: Inductor PCB Layout Isolation and Spacing

Evgeniy Sokolov
Intellectual 630 points
Part Number: TPS563200
Other Parts Discussed in Thread: TPS565208

Hello Community,

1. Tell me, is it necessary to isolate (cut copper) the area (placement area) located directly under the inductance from any passing signals, for example, from passing GND? (yellow border)
2. Is it necessary to indent elements of topology (capacitors, etc.) from the inductor if it is fully shielded? If so, what should be its value? (red arrow)

Description:

Left - Capacitor (VIN), Right - Inductor (VOUT) 

  • 0
    TI__Expert 4875 points
    HI Evgeniy,

    It is not necessary to isolate the plane especially for GND. GND plane will carry the return signal and the return signal should return with a smallest loop. What you may need to care about more is the SW polygon. Please make it smallest as possible. High dv/dt will induce capacitive coupling to other traces thru air.

    And it is not very critical to care about the distance between Vin cap and inductor. Like I mentioned in another post, the input cap should be kept close to device and make Vin and GND trace shorter. Thanks!
  • 0 in reply to Anthony Lang
    Intellectual 630 points

    Hello Anthony,

    1. Please tell me how to choose the correct value of inductance to voltage, which is not in the table (3.8V). Webbench selects 2.2uH. But I would like to understand by what principle this is happening.

    2. What principle is chosen for irms / isat inductors, what should be the supply of these values compared with irms / ipeak obtained in the calculations?

    3. Still could throw off the links describing di/dt, dv/dt?

  • 0 in reply to Evgeniy Sokolov
    TI__Expert 4875 points
    Hi Evgeniy,

    1. The inductor value could refer to 3.3V output voltage table and select 2.2uH or 3.3uH. The detailed explanation is in section 8.2.1.2.3 in datasheet. The main consideration is control loop stability and ripple current on inductor.

    2. Irms and Isat should be higher than the calculated value from datasheet equation. It will make sure inductor inductance is constant in all condition and inductor is cool.

    3. www.ti.com/.../slyy123.pdf
    training.ti.com/effect-high-didt-loops-emi
  • 0 in reply to Anthony Lang
    Intellectual 630 points

    Thank you for the information you provided! I studied everything in detail and I had the last questions.

    1. In the TPS563200 and TPS565208 Specifications, I noticed a different PCB layout, namely the top GND layer underneath the microcontroller. Do you think this is the right approach? (on the picture - red border) Can I use this approach in the case of the TPS563200? Will this technique increase EMI resistance?

    2. Why are none of the specifications near the GND pin having transfer holes when each capacitor has 2 pieces on each? Are vias needed to reduce the current trace near the output of the GND converter (PIN # 1)?

    3. Can I use ECAS (Murata) series polymer capacitors as output capacitors? 

    4. WebBench contains errors regarding the number of required capacitors provided by the specification. Example: instead of 2 output capacitors, it puts 1 on their total capacity. Please correct this.

  • 0 in reply to Evgeniy Sokolov
    TI__Expert 4875 points
    Hi Evgeniy,

    1. I would recommend you to follow with TPS565208 layout like the picture. We compare different layout and find this one has minimum small loop for di/dt loop.

    2. All the input current and output current will return to GND pin. Vias could help to shorten the loop.

    3. Yes, but it could have higher ESR and it could introduce more output ripple.

    4. I think Webench could only show you a guide on how much capacitance to put. Usually you could use several caps in parallel to get the same total output cap.