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BQ24780S: Minimum off time of high-side FET

Tamio Yokokura
Expert 3960 points
Part Number: BQ24780S

What is the minimum off time of high-side FET? When I saw other thread, it is 75nsec. If the off-time is depending on the switching frequency, please teach me about the minimum off-time of each switching frequency.

Regards,

Tamio

  • 0
    TI__Genius 11850 points

    Hi Tamio-san,

    The length of time that the HSFET is off can be expressed as HIDRV,off = (1 - D)*T

    Since D = Vout/Vin and T = 1/f, we can rewrite this as HIDRV,off = (1 - Vout/Vin)*(1/f) = (Vin - Vout)/(f*Vin)

    In order to minimize the HSFET off time, the expression above must be minimized. Therefore, f should be set to the maximum frequency of 1 MHz, and Vout should be set to the maximum value of 19.2 V. Using similar analysis to the thread you referenced (https://e2e.ti.com/support/power-management/f/196/t/609140?BQ24780S-Maxumum-duty-cycle), we will also assume that the forward drop of the Schottky diode is 0.4 V. Using the typical VCC_SRN falling threshold value of 60 mV, then the minimum Vin = 19.2 + 0.4 + 0.06 = 19.66 V, giving us a minimum HIDRV off time of:

    HIDRV,off = (Vin - Vout)/(f*Vin) = (19.66 - 19.2)/(1000000*19.66) = 23.4 ns

    Please note that this result may be slightly inaccurate due to the assumptions made, but it should help provide a rough estimate.

    Best regards,
    Angelo

  • 0 in reply to Angelo Zhang87
    TI__Expert 3960 points

    Hi, Angelo

    I appreciate your support.

    I understood about the thinking method of the minimum off-time by your advice. But I would like to know about the design value in the system design specification.

    • Is the minimum off-time the fixed value or not?
    • If YES, what is it?
    • If No, what is it depending on? 

    Thanks

    Tamio

  • 0 in reply to Tamio Yokokura
    TI__Genius 11850 points

    Hi Tamio-san,

    The minimum off-time is not a fixed value for the BQ24780S. It depends on several factors: input voltage, output voltage, frequency, dead time, and BTST refresh. Dead time and BTST refresh limit the maximum duty cycle of the HSFET and thus increase its minimum off-time.

    Best regards,

    Angelo